PATCH: Add Intel Xsave support
H.J. Lu
hjl.tools@gmail.com
Tue Feb 12 00:01:00 GMT 2008
I am checking in this patch to add Intel Xsave support:
http://www.intel.com/products/processor/manuals/index.htm
H.J.
--- binutils/gas/testsuite/ChangeLog.xsave 2008-02-11 15:53:49.000000000 -0800
+++ binutils/gas/testsuite/ChangeLog 2008-02-11 15:51:13.000000000 -0800
@@ -1,3 +1,15 @@
+2002-02-11 H.J. Lu <hongjiu.lu@intel.com>
+
+ * gas/i386/i386.exp: Run xsave, xsave-intel, x86-64-xsave
+ and x86-64-xsave-intel.
+
+ * gas/i386/x86-64-xsave-intel.d: New file.
+ * gas/i386/x86-64-xsave.d: Likewise.
+ * gas/i386/x86-64-xsave.s: Likewise.
+ * gas/i386/xsave-intel.d: Likewise.
+ * gas/i386/xsave.d: Likewise.
+ * gas/i386/xsave.s: Likewise.
+
2008-02-05 Adam Nemet <anemet@caviumnetworks.com>
* gas/mips/mips.exp: Invoke the tests smartmips, mips32-dsp,
--- binutils/gas/testsuite/gas/i386/i386.exp.xsave 2008-01-25 09:01:03.000000000 -0800
+++ binutils/gas/testsuite/gas/i386/i386.exp 2008-02-11 15:36:30.000000000 -0800
@@ -114,6 +114,8 @@ if [expr ([istarget "i*86-*-*"] || [ist
run_list_test "arch-10-4" "-march=i686+sse4+vmx+smx -I${srcdir}/$subdir -al"
run_dump_test "arch-11"
run_dump_test "arch-12"
+ run_dump_test "xsave"
+ run_dump_test "xsave-intel"
# These tests require support for 8 and 16 bit relocs,
# so we only run them for ELF and COFF targets.
@@ -226,6 +228,8 @@ if [expr ([istarget "i*86-*-*"] || [ista
run_dump_test "rexw"
run_dump_test "x86-64-arch-1"
run_dump_test "x86-64-arch-10"
+ run_dump_test "x86-64-xsave"
+ run_dump_test "x86-64-xsave-intel"
if { ![istarget "*-*-aix*"]
&& ![istarget "*-*-beos*"]
--- binutils/gas/testsuite/gas/i386/x86-64-xsave-intel.d.xsave 2008-02-11 15:35:26.000000000 -0800
+++ binutils/gas/testsuite/gas/i386/x86-64-xsave-intel.d 2008-02-11 15:40:04.000000000 -0800
@@ -0,0 +1,17 @@
+#source: x86-64-xsave.s
+#as: -J
+#objdump: -dw -Mintel
+#name: x86-64 xsave (Intel mode)
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+: 41 0f ae 29 xrstor \[r9\]
+[ ]*[a-f0-9]+: 41 0f ae 21 xsave \[r9\]
+[ ]*[a-f0-9]+: 0f 01 d0 xgetbv
+[ ]*[a-f0-9]+: 0f 01 d1 xsetbv
+[ ]*[a-f0-9]+: 0f ae 29 xrstor \[rcx\]
+[ ]*[a-f0-9]+: 0f ae 21 xsave \[rcx\]
+#pass
--- binutils/gas/testsuite/gas/i386/x86-64-xsave.d.xsave 2008-02-11 15:35:26.000000000 -0800
+++ binutils/gas/testsuite/gas/i386/x86-64-xsave.d 2008-02-11 15:39:59.000000000 -0800
@@ -0,0 +1,15 @@
+#objdump: -dw
+#name: x86-64 xsave prefix
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+: 41 0f ae 29 xrstor \(%r9\)
+[ ]*[a-f0-9]+: 41 0f ae 21 xsave \(%r9\)
+[ ]*[a-f0-9]+: 0f 01 d0 xgetbv
+[ ]*[a-f0-9]+: 0f 01 d1 xsetbv
+[ ]*[a-f0-9]+: 0f ae 29 xrstor \(%rcx\)
+[ ]*[a-f0-9]+: 0f ae 21 xsave \(%rcx\)
+#pass
--- binutils/gas/testsuite/gas/i386/x86-64-xsave.s.xsave 2008-02-11 15:35:26.000000000 -0800
+++ binutils/gas/testsuite/gas/i386/x86-64-xsave.s 2008-02-11 15:40:09.000000000 -0800
@@ -0,0 +1,11 @@
+# Check 64bit xsave/xrstor
+ .text
+_start:
+ xrstor (%r9)
+ xsave (%r9)
+ xgetbv
+ xsetbv
+
+ .intel_syntax noprefix
+ xrstor [rcx]
+ xsave [rcx]
--- binutils/gas/testsuite/gas/i386/xsave-intel.d.xsave 2008-02-11 15:35:26.000000000 -0800
+++ binutils/gas/testsuite/gas/i386/xsave-intel.d 2008-02-11 15:39:21.000000000 -0800
@@ -0,0 +1,17 @@
+#source: xsave.s
+#as: -J
+#objdump: -dw -Mintel
+#name: i386 xsave (Intel mode)
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+: 0f ae 2b xrstor \[ebx\]
+[ ]*[a-f0-9]+: 0f ae 23 xsave \[ebx\]
+[ ]*[a-f0-9]+: 0f 01 d0 xgetbv
+[ ]*[a-f0-9]+: 0f 01 d1 xsetbv
+[ ]*[a-f0-9]+: 0f ae 29 xrstor \[ecx\]
+[ ]*[a-f0-9]+: 0f ae 21 xsave \[ecx\]
+#pass
--- binutils/gas/testsuite/gas/i386/xsave.d.xsave 2008-02-11 15:35:26.000000000 -0800
+++ binutils/gas/testsuite/gas/i386/xsave.d 2008-02-11 15:39:24.000000000 -0800
@@ -0,0 +1,15 @@
+#objdump: -dw
+#name: i386 xsave
+
+.*: file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+: 0f ae 2b xrstor \(%ebx\)
+[ ]*[a-f0-9]+: 0f ae 23 xsave \(%ebx\)
+[ ]*[a-f0-9]+: 0f 01 d0 xgetbv
+[ ]*[a-f0-9]+: 0f 01 d1 xsetbv
+[ ]*[a-f0-9]+: 0f ae 29 xrstor \(%ecx\)
+[ ]*[a-f0-9]+: 0f ae 21 xsave \(%ecx\)
+#pass
--- binutils/gas/testsuite/gas/i386/xsave.s.xsave 2008-02-11 15:35:26.000000000 -0800
+++ binutils/gas/testsuite/gas/i386/xsave.s 2008-02-11 15:39:31.000000000 -0800
@@ -0,0 +1,11 @@
+# Check xsave/xrstor
+ .text
+_start:
+ xrstor (%ebx)
+ xsave (%ebx)
+ xgetbv
+ xsetbv
+
+ .intel_syntax noprefix
+ xrstor [ecx]
+ xsave [ecx]
--- binutils/opcodes/ChangeLog.xsave 2008-02-11 15:53:49.000000000 -0800
+++ binutils/opcodes/ChangeLog 2008-02-11 15:50:40.000000000 -0800
@@ -1,3 +1,24 @@
+2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (cpu_flags): Add CpuXsave.
+
+ * i386-opc.h (CpuXsave): New.
+ (Cpu64): Updated.
+ (i386_cpu_flags): Add cpuxsave.
+
+ * i386-dis.c (MOD_0FAE_REG_4): New.
+ (RM_0F01_REG_2): Likewise.
+ (MOD_0FAE_REG_5): Updated.
+ (RM_0F01_REG_3): Likewise.
+ (reg_table): Use MOD_0FAE_REG_4.
+ (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
+ for xrstor.
+ (rm_table): Add RM_0F01_REG_2.
+
+ * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
2008-02-11 Jan Beulich <jbeulich@novell.com>
* i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
--- binutils/opcodes/i386-dis.c.xsave 2008-01-25 09:01:03.000000000 -0800
+++ binutils/opcodes/i386-dis.c 2008-02-11 15:50:29.000000000 -0800
@@ -542,7 +542,8 @@ fetch_data (struct disassemble_info *inf
#define MOD_0FAE_REG_1 (MOD_0FAE_REG_0 + 1)
#define MOD_0FAE_REG_2 (MOD_0FAE_REG_1 + 1)
#define MOD_0FAE_REG_3 (MOD_0FAE_REG_2 + 1)
-#define MOD_0FAE_REG_5 (MOD_0FAE_REG_3 + 1)
+#define MOD_0FAE_REG_4 (MOD_0FAE_REG_3 + 1)
+#define MOD_0FAE_REG_5 (MOD_0FAE_REG_4 + 1)
#define MOD_0FAE_REG_6 (MOD_0FAE_REG_5 + 1)
#define MOD_0FAE_REG_7 (MOD_0FAE_REG_6 + 1)
#define MOD_0FB2 (MOD_0FAE_REG_7 + 1)
@@ -560,7 +561,8 @@ fetch_data (struct disassemble_info *inf
#define RM_0F01_REG_0 0
#define RM_0F01_REG_1 (RM_0F01_REG_0 + 1)
-#define RM_0F01_REG_3 (RM_0F01_REG_1 + 1)
+#define RM_0F01_REG_2 (RM_0F01_REG_1 + 1)
+#define RM_0F01_REG_3 (RM_0F01_REG_2 + 1)
#define RM_0F01_REG_7 (RM_0F01_REG_3 + 1)
#define RM_0FAE_REG_5 (RM_0F01_REG_7 + 1)
#define RM_0FAE_REG_6 (RM_0FAE_REG_5 + 1)
@@ -1764,7 +1766,7 @@ static const struct dis386 reg_table[][8
{ MOD_TABLE (MOD_0FAE_REG_1) },
{ MOD_TABLE (MOD_0FAE_REG_2) },
{ MOD_TABLE (MOD_0FAE_REG_3) },
- { "(bad)", { XX } },
+ { MOD_TABLE (MOD_0FAE_REG_4) },
{ MOD_TABLE (MOD_0FAE_REG_5) },
{ MOD_TABLE (MOD_0FAE_REG_6) },
{ MOD_TABLE (MOD_0FAE_REG_7) },
@@ -4549,7 +4551,7 @@ static const struct dis386 mod_table[][2
{
/* MOD_0F01_REG_2 */
{ X86_64_TABLE (X86_64_0F01_REG_2) },
- { "(bad)", { XX } },
+ { RM_TABLE (RM_0F01_REG_2) },
},
{
/* MOD_0F01_REG_3 */
@@ -4727,8 +4729,13 @@ static const struct dis386 mod_table[][2
{ "(bad)", { XX } },
},
{
- /* MOD_0FAE_REG_5 */
+ /* MOD_0FAE_REG_4 */
+ { "xsave", { M } },
{ "(bad)", { XX } },
+ },
+ {
+ /* MOD_0FAE_REG_5 */
+ { "xrstor", { M } },
{ RM_TABLE (RM_0FAE_REG_5) },
},
{
@@ -4827,6 +4834,17 @@ static const struct dis386 rm_table[][8]
{ "(bad)", { XX } },
},
{
+ /* RM_0F01_REG_2 */
+ { "xgetbv", { Skip_MODRM } },
+ { "xsetbv", { Skip_MODRM } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ },
+ {
/* RM_0F01_REG_3 */
{ "vmrun", { Skip_MODRM } },
{ "vmmcall", { Skip_MODRM } },
--- binutils/opcodes/i386-gen.c.xsave 2008-01-25 09:01:03.000000000 -0800
+++ binutils/opcodes/i386-gen.c 2008-02-11 15:35:28.000000000 -0800
@@ -245,6 +245,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuSMX),
BITFIELD (CpuABM),
BITFIELD (CpuLM),
+ BITFIELD (CpuXsave),
BITFIELD (Cpu64),
BITFIELD (CpuNo64),
#ifdef CpuUnused
--- binutils/opcodes/i386-opc.h.xsave 2008-01-22 11:57:43.000000000 -0800
+++ binutils/opcodes/i386-opc.h 2008-02-11 15:35:28.000000000 -0800
@@ -80,8 +80,10 @@
#define CpuSSE4_2 (CpuSSE4_1 + 1)
/* SSE5 support required */
#define CpuSSE5 (CpuSSE4_2 + 1)
+/* Xsave/xrstor New Instuctions support required */
+#define CpuXsave (CpuSSE5 + 1)
/* 64bit support available, used by -march= in assembler. */
-#define CpuLM (CpuSSE5 + 1)
+#define CpuLM (CpuXsave + 1)
/* 64bit support required */
#define Cpu64 (CpuLM + 1)
/* Not supported in the 64bit mode */
@@ -129,6 +131,7 @@ typedef union i386_cpu_flags
unsigned int cpusse4_1:1;
unsigned int cpusse4_2:1;
unsigned int cpusse5:1;
+ unsigned int cpuxsave:1;
unsigned int cpulm:1;
unsigned int cpu64:1;
unsigned int cpuno64:1;
--- binutils/opcodes/i386-opc.tbl.xsave 2008-02-11 15:30:35.000000000 -0800
+++ binutils/opcodes/i386-opc.tbl 2008-02-11 15:37:05.000000000 -0800
@@ -1408,6 +1408,13 @@ crc32, 2, 0xf20f38f1, None, 3, CpuSSE4_2
crc32, 2, 0xf20f38f0, None, 3, CpuSSE4_2, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 }
crc32, 2, 0xf20f38f0, None, 3, CpuSSE4_2|Cpu64, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, Reg64 }
+// xsave/xrstor New Instructions.
+
+xsave, 1, 0xfae, 0x4, 2, CpuXsave, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+xrstor, 1, 0xfae, 0x5, 2, CpuXsave, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+xgetbv, 0, 0xf01, 0xd0, 2, CpuXsave, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
+xsetbv, 0, 0xf01, 0xd1, 2, CpuXsave, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
+
// AMD 3DNow! instructions.
prefetch, 1, 0xf0d, 0x0, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
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