COMMITTED: Fix typo in DREM macros in the MIPS opcode table

Adam Nemet anemet@caviumnetworks.com
Wed Apr 30 03:51:00 GMT 2008


Thiemo Seufer writes:
> Adam Nemet wrote:
> > Another option would be to use the match field which as far as I know
> > should always be zero for macros.  (Confusingly enough, the drem macros
> > have 3 as their match field.  Is that a typo?)
> 
> Looks like a typo to me.

I looked through the sources whether this magic value was used anywere.  Also
there is a test div which seems to provide good coverage for DREM* which still
passes after the fix.

I checked in this patch as obvious after testing it on mips64octeon-linux-gnu.

Adam


2008-04-29  Adam Nemet  <anemet@caviumnetworks.com>

	* mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
	the two drem and the two dremu macros.

Index: mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.66
diff -F^\([(a-zA-Z0-9_]\|#define\) -u -p -u -r1.66 mips-opc.c
--- mips-opc.c	28 Apr 2008 17:03:58 -0000	1.66
+++ mips-opc.c	29 Apr 2008 23:01:47 -0000
@@ -630,11 +630,11 @@ const struct mips_opcode mips_builtin_op
 {"dneg",    "d,w",	0x0000002e, 0xffe007ff,	WR_d|RD_t,		0,		I3	}, /* dsub 0 */
 {"dnegu",   "d,w",	0x0000002f, 0xffe007ff,	WR_d|RD_t,		0,		I3	}, /* dsubu 0*/
 {"drem",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I3      },
-{"drem",    "d,v,t",	3,    (int) M_DREM_3,	INSN_MACRO,		0,		I3	},
-{"drem",    "d,v,I",	3,    (int) M_DREM_3I,	INSN_MACRO,		0,		I3	},
+{"drem",    "d,v,t",	0,    (int) M_DREM_3,	INSN_MACRO,		0,		I3	},
+{"drem",    "d,v,I",	0,    (int) M_DREM_3I,	INSN_MACRO,		0,		I3	},
 {"dremu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I3      },
-{"dremu",   "d,v,t",	3,    (int) M_DREMU_3,	INSN_MACRO,		0,		I3	},
-{"dremu",   "d,v,I",	3,    (int) M_DREMU_3I,	INSN_MACRO,		0,		I3	},
+{"dremu",   "d,v,t",	0,    (int) M_DREMU_3,	INSN_MACRO,		0,		I3	},
+{"dremu",   "d,v,I",	0,    (int) M_DREMU_3I,	INSN_MACRO,		0,		I3	},
 {"dret",    "",		0x7000003e, 0xffffffff,	0,			0,		N5	},
 {"drol",    "d,v,t",	0,    (int) M_DROL,	INSN_MACRO,		0,		I3	},
 {"drol",    "d,v,I",	0,    (int) M_DROL_I,	INSN_MACRO,		0,		I3	},





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