PATCH: PR 658: i386 assembler and disassembler can't handle SIB with INDEX==4

[Jan Beulich]

>> It turns out that Intel assembler uses EIZ/RIZ as fake index
>> registers for this purpose. This patch adds a new directive,
>> .allow_index_reg, which will allow EIZ/RIZ as index registers.
>> Are there any comments?
>> 
>> Thanks.
>> 
>
>Here is the updated patch. It displays EIZ/RIZ only when there
>is an ambiguity. That is "BASE" and "BASE + EIZ/RIZ" have different
>opcodes.

I think that on the assembler end, using %eiz is fine, but on the disassembler
side this pseudo register shouldn't be displayed unless absolutely needed (i.e.

[	 ]*12:[	 ]+8d b4 26 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi,%eiz,1\),%esi

should be

[	 ]*12:[	 ]+8d b4 26 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi,,1\),%esi

or

[	 ]*12:[	 ]+8d b4 26 00 00 00 00[	 ]+lea[ 	]+0x0\(%esi,1\),%esi

depending on what appears to make more sense. Perhaps even more reasonably
we could introduce a new option (or tie this to suffix_always), and by default
retain the old behavior. With the option enabled, you could then of course always
display the fake index.

Jan