[PATCH] S/390: Add new z9-ec instructions.

[Andreas Krebbel]

Hi,

with a new firmware level the z9 server series got several new instructions.
These instructions are documented here:
http://publibz.boulder.ibm.com/epubs/pdf/a2278325.pdf

Most of the new instructions are part of the decimal floating point facility
and were described in a preliminary document.  This patch adds the instructions
missing in the preliminary document to the binutils package.

Most important for us currently is the pfpo instruction which is able to convert
between different floating point formats.

Binutils built. No testsuite fails.

Ok?

Bye,

-Andreas-


2007-04-24  Andreas Krebbel  <krebbel1@de.ibm.com>

	* opcodes/s390-opc.c (MASK_SSF_RRDRD): Fourth nybble belongs to the
	opcode.
	* opcodes/s390-opc.txt (pfpo, ectg, csst): New z9-ec instructions added.


2007-04-24  Andreas Krebbel  <krebbel1@de.ibm.com>

	* gas/s390/zarch-z9-ec.d: Add pfpo, ectg and csst.
	* gas/s390/zarch-z9-ec.s: Likewise.


Index: opcodes/s390-opc.txt
===================================================================
*** opcodes/s390-opc.txt.orig	2007-04-24 14:54:49.000000000 +0200
--- opcodes/s390-opc.txt	2007-04-24 14:55:11.000000000 +0200
*************** ed0000000058 tcxt RXE_FRRD "test data cl
*** 926,928 ****
--- 926,931 ----
  ed0000000051 tget RXE_FRRD "test data group short dfp" z9-ec zarch
  ed0000000055 tgdt RXE_FRRD "test data group long dfp" z9-ec zarch
  ed0000000059 tgxt RXE_FRRD "test data group extended dfp" z9-ec zarch
+ 010a pfpo E "perform floating point operation" z9-ec zarch
+ c801 ectg SSF_RRDRD "extract cpu time" z9-ec zarch
+ c802 csst SSF_RRDRD "compare and swap and store" z9-ec zarch
Index: opcodes/s390-opc.c
===================================================================
*** opcodes/s390-opc.c.orig	2007-04-24 14:54:49.000000000 +0200
--- opcodes/s390-opc.c	2007-04-24 14:55:11.000000000 +0200
*************** const struct s390_operand s390_operands[
*** 345,351 ****
  #define MASK_SS_RRRDRD3  { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
  #define MASK_S_00        { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
  #define MASK_S_RD        { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
! #define MASK_SSF_RRDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
  
  /* The opcode formats table (blueprints for .insn pseudo mnemonic).  */
  
--- 345,351 ----
  #define MASK_SS_RRRDRD3  { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
  #define MASK_S_00        { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
  #define MASK_S_RD        { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
! #define MASK_SSF_RRDRD   { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
  
  /* The opcode formats table (blueprints for .insn pseudo mnemonic).  */
  
Index: gas/testsuite/gas/s390/zarch-z9-ec.d
===================================================================
*** gas/testsuite/gas/s390/zarch-z9-ec.d.orig	2007-04-24 14:54:49.000000000 +0200
--- gas/testsuite/gas/s390/zarch-z9-ec.d	2007-04-24 15:16:14.000000000 +0200
*************** Disassembly of section .text:
*** 69,71 ****
--- 69,76 ----
  .*:	ed 61 20 03 00 51 [	 ]*tget	%f6,3\(%r1,%r2\)
  .*:	ed 61 20 03 00 55 [	 ]*tgdt	%f6,3\(%r1,%r2\)
  .*:	ed 61 20 03 00 59 [	 ]*tgxt	%f6,3\(%r1,%r2\)
+ .*:	01 0a [	 ]*pfpo
+ .*:	c8 31 10 0a 20 14 [	 ]*ectg	10\(%r1\),20\(%r2\),%r3
+ .*:	c8 32 10 0a 20 14 [	 ]*csst	10\(%r1\),20\(%r2\),%r3
+ # Expect 2 bytes of padding.
+ .*:	07 07 [	 ]*bcr	0,%r7
Index: gas/testsuite/gas/s390/zarch-z9-ec.s
===================================================================
*** gas/testsuite/gas/s390/zarch-z9-ec.s.orig	2007-04-24 14:54:49.000000000 +0200
--- gas/testsuite/gas/s390/zarch-z9-ec.s	2007-04-24 15:18:45.000000000 +0200
*************** foo:
*** 63,65 ****
--- 63,72 ----
  	tget	%f6,3(%r1,%r2)
  	tgdt	%f6,3(%r1,%r2)
  	tgxt	%f6,3(%r1,%r2)
+ 	pfpo
+ 	ectg	10(%r1),20(%r2),%r3
+ 	csst	10(%r1),20(%r2),%r3
+ 	/* The following .data section is 4 byte aligned.
+ 	   So we get 2 additional bytes of 07 07 wherefor
+ 	   we have to provide an instruction.  */
+ 	bcr	0,%r7