Allow rsbs in Thumb-1 code

[Paul Brook]

The patch below allows the rsb/rsbs instructions on Thumb-1 cores. Limited 
forms of these mnemonics result in Thumb-1 instructions.

Testcase will be included in my next patch.

Tested on arm-none-eabi.
Applied to CVS head.

Paul

2007-04-19  Paul Brook  <paul@codesourcery.com>

	gas/
	* config/tc-arm.c (insns): Allow rsb and rsbs on Thumb-1.

Index: gas/config/tc-arm.c
===================================================================
--- gas/config/tc-arm.c	(revision 169208)
+++ gas/config/tc-arm.c	(working copy)
@@ -14790,6 +14804,10 @@ static const struct asm_opcode insns[] =
  tCE(push,	92d0000, push,     1, (REGLST),	     push_pop, t_push_pop),
  tCE(pop,	8bd0000, pop,	   1, (REGLST),	     push_pop, t_push_pop),
 
+ /* These may simplify to neg.  */
+ TCE(rsb,	0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
+ TC3(rsbs,	0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
+
 #undef THUMB_VARIANT
 #define THUMB_VARIANT &arm_ext_v6
  TCE(cpy,       1a00000, 4600,     2, (RR, RR),      rd_rm, t_cpy),
@@ -14797,8 +14815,6 @@ static const struct asm_opcode insns[] =
  /* V1 instructions with no Thumb analogue prior to V6T2.  */
 #undef THUMB_VARIANT
 #define THUMB_VARIANT &arm_ext_v6t2
- TCE(rsb,	0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
- TC3(rsbs,	0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
  TCE(teq,	1300000, ea900f00, 2, (RR, SH),      cmp,  t_mvn_tst),
  TC3(teqs,	1300000, ea900f00, 2, (RR, SH),      cmp,  t_mvn_tst),
   CL(teqp,	130f000,           2, (RR, SH),      cmp),