Problem with AMD64 ld with linker script
Fri Oct 6 05:09:00 GMT 2006
On 06/10/06, Daniel Jacobowitz <firstname.lastname@example.org> wrote:
> On Thu, Oct 05, 2006 at 07:00:33PM +0200, Peter Bindels wrote:
> > As soon as I use a linker script, the alignments for all sections
> > immediately jump to 2^20, with no possible way to get the alignment
> > down. As a result of that, the .text is at 0x100000, .data is at
> > 0x200000 and .init (kernel-specific section) is at 0x300000. That
> > results in a binary over 3 megabytes in size, albeit very sparse,
> > where I wanted about a 64k binary.
> I experimented with this. It's doing what you asked it to. It's the
> maximum legal page size being enforced: you can't map pages from the
> binary file to the right VMAs if they're misaligned in the file
> relative to the page size. You'll see that using ld -N completely
> eliminates them. That may be the right answer for your usage, if
> you aren't interested in dynamic paging.
> You asked for your PHDRs to be at 0x100000 intervals. To put sections
> in them, you're going to have to align them at file offsets equal to
> their VMAs, modulus 0x100000. Which is not what you really want, is
I was considering it to do that, but since the target arch only has
pages of 4 kbyte and 2 megabyte, I counted this out. The PHDRS were a
tryout and didn't do anything functional, you could leave them out
(and align the sections' load addresses equally). Where does it get
the megabyte alignment idea, other than the PHDRS?
To be honest, I was interested in dynamic paging but at a 4k interval.
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