[m68k] arch flag cleanup v2

[Nathan Sidwell]

This patch reworks some of the changes I made in my last patch to cleanup the 
coldfire architecture switches.  In re-reviewing the coldfire architectures, and 
the bfd_mach enumeration, I realized we'd been too flexible, and this was 
confusing.  AFAICT all isa-a machines implement hw div (an isa-a insn), except 
for 5200, 5202, 5204 & 5206.  Rather than have a separate ELF flag for hwdiv, 
this patch creates a variant isa 'a-minus', which is all of isa-a except for the 
hwdiv insns.  similarly all isa-a+ & isa-b chips implement USP support except 
for 5407.  Thus I enumerated an isa-b-minus variant in the ELF flags for that.
These new isa names are user visible, in that objdump and readelf will show 
them.  The user cannot select them directly (use isaa,nohwdiv and isab,nousp 
respectively).  I could rework the display so that what I've termed isa-a-minus 
is shown as '[isa-a] [nohwdiv]' for instance.  I have no strong feeling about 
that, except a negative capability flag might be a bit odd.

This elf flag relabling is binary incompatible with the previous version, but as 
that's only been committed for a couple of weeks, I think that is ok.

The patch also fixes an error in merging the elf flags, in that isa-a+ and isa-b 
are not compatible.

Also, this patch allows -mfloat to be used to enable either cf-float or 
m68k-float (68881) support, depending on the architecture being targetted. This 
capability will be used in upcoming gcc patches.

built & tested on m68k-elf with a cf simulator, ok?

nathan
-- 
Nathan Sidwell    ::   http://www.codesourcery.com   ::         CodeSourcery
nathan@codesourcery.com    ::     http://www.planetfall.pwp.blueyonder.co.uk

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