RFA: arm maverick disassembly

[Richard Earnshaw]

On Sat, 2005-10-08 at 15:54, Richard Earnshaw wrote:
> On Fri, 2005-10-07 at 22:44, James Lemke wrote:
> > I got a report of incorrect disassembly of mrc opcodes as cfmsub32.
> > E.G.
> > was         ee102610    cfmsub32    mvax0, mvfx2, mvfx0, mvfx0
> > should be   ee102610    mrc     6, 0, r2, cr0, cr0, {0}
> > 
> > I found that 6 of the Maverick CDP opcodes do not depend on bit 4 when
> > they should.  Patch attached.
> > 
> > Tested on x86-linux x arm-elf.
> > No change in binutils results.
> > gcc results had no regressions and 15 improvements:
> > 2x unsupported -> pass  gcc.dg/cpp/trad/num-sign.c
> > 13x untested -> pass gcc.dg/pch/valid-[123].c & warn-1.c
> > 
> > Not sure that this qualifies for the "obvious" rule.
> > OK to commit?
> 
> Thanks, I've put this in after updating it to the current sources.
> 
> For future reference, please don't send ChangeLog entries as diff
> output, they almost never apply cleanly.

Unfortunately this tripped a bug in the gas testsuite.  Fixed thusly:

2005-10-17  Richard Earnshaw  <richard.earnshaw@arm.com>

	* gas/arm/copro.d: 'mcrlt' instruction should not be disassembled as
	'cfsh64lt'.




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