RFA: arm maverick disassembly

[James Lemke]

I got a report of incorrect disassembly of mrc opcodes as cfmsub32.
E.G.
was         ee102610    cfmsub32    mvax0, mvfx2, mvfx0, mvfx0
should be   ee102610    mrc     6, 0, r2, cr0, cr0, {0}

I found that 6 of the Maverick CDP opcodes do not depend on bit 4 when
they should.  Patch attached.

Tested on x86-linux x arm-elf.
No change in binutils results.
gcc results had no regressions and 15 improvements:
2x unsupported -> pass  gcc.dg/cpp/trad/num-sign.c
13x untested -> pass gcc.dg/pch/valid-[123].c & warn-1.c

Not sure that this qualifies for the "obvious" rule.
OK to commit?

-- 
Jim Lemke   jim@wasabisystems.com   Orillia, Ontario
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