MIPS R5900 support => Disabling a few I2 instructions

[Thiemo Seufer]

Doug Evans wrote:
[snip]
>  > That's why I chose to define it as a MIPS3 CPU.
>  > 
>  > When I look in opcodes/mips-opc.c, I see a lot of ways to add
>  > instructions to a certain CPU, but I can't find a way to just disable
>  > ll/lld/sc/scd (I can't just say I2&!T59 or something).
>  > 
>  > What would be the best way to disable ll/lld/sc/scd *only* on the MIPS
>  > R5900?

That's not supported, because an CPU is supposed to provide all the
instructions the ISA defines. AFAICS you should use MIPS I ISA, and
add a R5900-specific flag, so you can say e.g. I1 | EE.

> I'm confused by "That's why I chose to define it as a MIPS3 CPU."
> 
> That suggests all of Cygnus's work circa 1998/1999 didn't get
> folded back into the FSF tree.  I know the dvp stuff didn't get
> folded back :-(, but the mips stuff too?

There are quite a lot of patches from various embedded mips toolchains
which never found their way in the FSF tree.


Thiemo