[patch ping] GAS supports for MIPS32 DSP ASE

Chao-ying Fu fu@mips.com
Wed Aug 17 18:32:00 GMT 2005


Thanks for your review!

1. The bitmasks are used up to 0x02000000,
so I used 0x04000000 for INSN_DSP.
But, after examining all INSN_*, I could use 
0x00001000 for INSN_DSP, because it is still 
available.  Do you prefer changing it to 0x00001000?

Ex: 
#define INSN_ISA_MASK             0x00000fff
#define INSN_ISA1                 0x00000001
#define INSN_ISA2                 0x00000002
#define INSN_ISA3                 0x00000004
#define INSN_ISA4                 0x00000008
#define INSN_ISA5                 0x00000010
#define INSN_ISA32                0x00000020
#define INSN_ISA64                0x00000040
#define INSN_ISA32R2              0x00000080
#define INSN_ISA64R2              0x00000100
#define INSN_ASE_MASK             0x0000f000
/* MIPS 16 ASE */
#define INSN_MIPS16               0x00002000
/* MIPS-3D ASE */
#define INSN_MIPS3D               0x00004000
/* MDMX ASE */
#define INSN_MDMX                 0x00008000
/* Chip specific instructions.  These are bitmasks.  */
/* MIPS R4650 instruction.  */
#define INSN_4650                 0x00010000
/* LSI R4010 instruction.  */
#define INSN_4010                 0x00020000
/* NEC VR4100 instruction.  */
#define INSN_4100                 0x00040000
/* Toshiba R3900 instruction.  */
#define INSN_3900                 0x00080000
/* MIPS R10000 instruction.  */
#define INSN_10000                0x00100000
/* Broadcom SB-1 instruction.  */
#define INSN_SB1                  0x00200000
/* NEC VR4111/VR4181 instruction.  */
#define INSN_4111                 0x00400000
/* NEC VR4120 instruction.  */
#define INSN_4120                 0x00800000
/* NEC VR5400 instruction.  */
#define INSN_5400                 0x01000000
/* NEC VR5500 instruction.  */
#define INSN_5500                 0x02000000

2. "bposge32" is a conditional branch which has
a delay slot, so I use CBD.  And, "bposge32" 
depends on the pos field of the DSP control register.
Thus, we only need to restrict instructions that write
to the pos field by setting DSP_VOLA for them.
(However, "bposge32" itself doesn't need DSP_VOLA.)
Is this ok?  Thanks!

Regards,
Chao-ying


----- Original Message ----- 
From: "Eric Christopher" <echristo@apple.com>
To: "Chao-ying Fu" <fu@mips.com>
Cc: <binutils@sourceware.org>; "Thiemo Seufer" <ths@networkno.de>
Sent: Tuesday, August 16, 2005 6:25 PM
Subject: Re: [patch ping] GAS supports for MIPS32 DSP ASE


> 
> On Aug 12, 2005, at 5:19 PM, Chao-ying Fu wrote:
> 
> *************** struct mips_opcode
> *** 411,417 ****
>    #define INSN_ISA64R2              0x00000100
> 
>    /* Masks used for MIPS-defined ASEs.  */
> ! #define INSN_ASE_MASK           0x0000f000
> 
>    /* MIPS 16 ASE */
>    #define INSN_MIPS16               0x00002000
> --- 447,453 ----
>    #define INSN_ISA64R2              0x00000100
> 
>    /* Masks used for MIPS-defined ASEs.  */
> ! #define INSN_ASE_MASK           0x0400f000
> 
>    /* MIPS 16 ASE */
>    #define INSN_MIPS16               0x00002000
> *************** struct mips_opcode
> *** 419,424 ****
> --- 455,462 ----
>    #define INSN_MIPS3D               0x00004000
>    /* MDMX ASE */
>    #define INSN_MDMX                 0x00008000
> + /* DSP ASE */
> + #define INSN_DSP                0x04000000
> 
> 
> Why?
> 
> + {"bposge32", "p",     0x041c0000, 0xffff0000,  
> CBD,                    0,              D32
>          },
> 
> CBD? And you didn't add the DSP_VOLA that you mentioned above.
> 
> Otherwise it looks good.
> 
> -eric
> 
> 



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