Thumb32 assembler (42/69)
Zack Weinberg
zack@codesourcery.com
Fri Apr 29 11:57:00 GMT 2005
Paul Brook <paul@codesourcery.com> writes:
> On Tuesday 26 April 2005 10:55, Zack Weinberg wrote:
>> constant handling is deferred to md_apply_fix3 so that code is not
>> duplicated between there and the encoder functions.
...
> Breaks the following assembly fragment:
>
> .text
> .code 16
> .align 2
> .global _start
> .thumb_func
> _start:
> ldr r0, foo
> ldr r0, foo
> ldr r0, [pc, #4]
> ldr r0, [pc, #4]
> foo:
> .word 42
I have attempted to fix this, but I have not been entirely successful.
When md_apply_fix3 is called, the second 'ldr r0, foo' has an
identical fix structure to that generated for 'ldr r0, [pc, #4]'.
This is because fixup_segment is not aware of the pipeline offset, it
having been coded into some (not all) of the relevant instructions
rather than expressed with md_pcrel_from. Accordingly I tried to
address the problem by using md_pcrel_from to express the pipeline
offset, instead of coding it into instructions. This works great for
the above test case, however, it breaks two gas test cases and three
ld test cases, and I have not been able to compensate.
The appended patch is as far as I've gotten. Note that some of the
changes to tc-arm.c and the testsuite are unrelated bugfixes which I
happened to notice while testing this patch - I let some incorrect
encodings slip past me into thumb32.d when I originally wrote it. The
changes to arm-dis.c merely add label annotations to Thumb32
PC-relative ldr disassembly.
Any help would be appreciated.
zw
===================================================================
Index: gas/config/tc-arm.c
--- gas/config/tc-arm.c (revision 85)
+++ gas/config/tc-arm.c (working copy)
@@ -465,7 +465,7 @@ struct asm_opcode
#define T_OPCODE_PUSH 0xb400
#define T_OPCODE_POP 0xbc00
-#define T_OPCODE_BRANCH 0xe7fe
+#define T_OPCODE_BRANCH 0xe000
#define THUMB_SIZE 2 /* Size of thumb instruction. */
#define THUMB_PP_PC_LR 0x0100
@@ -4051,8 +4051,6 @@ encode_arm_addr_mode_2 (int i, bfd_boole
{
if (inst.reloc.type == BFD_RELOC_UNUSED)
inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
- if (inst.reloc.pc_rel)
- inst.reloc.exp.X_add_number -= 8; /* pipeline offset */
}
}
@@ -4083,8 +4081,6 @@ encode_arm_addr_mode_3 (int i, bfd_boole
inst.instruction |= HWOFFSET_IMM;
if (inst.reloc.type == BFD_RELOC_UNUSED)
inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
- if (inst.reloc.pc_rel)
- inst.reloc.exp.X_add_number -= 8; /* pipeline offset */
}
}
@@ -4137,8 +4133,6 @@ encode_arm_cp_address (int i, int wb_ok,
inst.reloc.type = reloc_override;
else
inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
- if (inst.reloc.pc_rel)
- inst.reloc.exp.X_add_number -= 8;
return SUCCESS;
}
@@ -4305,9 +4299,6 @@ do_adr (void)
/* Frag hacking will turn this into a sub instruction if the offset turns
out to be negative. */
inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
-#ifndef TE_WINCE
- inst.reloc.exp.X_add_number -= 8; /* PC relative adjust. */
-#endif
inst.reloc.pc_rel = 1;
}
@@ -4324,9 +4315,6 @@ do_adrl (void)
/* Frag hacking will turn this into a sub instruction if the offset turns
out to be negative. */
inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
-#ifndef TE_WINCE
- inst.reloc.exp.X_add_number -= 8; /* PC relative adjust */
-#endif
inst.reloc.pc_rel = 1;
inst.size = INSN_SIZE * 2;
}
@@ -4408,13 +4396,10 @@ encode_branch (int default_reloc)
constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32,
_("the only suffix valid here is '(plt)'"));
inst.reloc.type = BFD_RELOC_ARM_PLT32;
- inst.reloc.pc_rel = 0;
}
else
- {
- inst.reloc.type = default_reloc;
- inst.reloc.pc_rel = 1;
- }
+ inst.reloc.type = default_reloc;
+ inst.reloc.pc_rel = 1;
}
static void
@@ -4448,7 +4433,7 @@ do_blx (void)
/* Arg is an address; this instruction cannot be executed
conditionally, and the opcode must be adjusted. */
constraint ((inst.instruction & COND_MASK) != COND_ALWAYS, BAD_COND);
- inst.instruction = 0xfafffffe;
+ inst.instruction = 0xfa000000;
encode_branch (BFD_RELOC_ARM_PCREL_BLX);
}
}
@@ -5639,6 +5624,7 @@ encode_thumb32_addr_mode (int i, bfd_boo
inst.instruction |= 0x00000100;
}
inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
+ inst.reloc.pc_rel = is_pc;
}
else if (inst.operands[i].postind)
{
@@ -5672,7 +5658,6 @@ encode_thumb32_addr_mode (int i, bfd_boo
X(asrs, 1000, fa50f000), \
X(bic, 4380, ea200000), \
X(bics, 4380, ea300000), \
- X(blx, 4780, f000c000), \
X(cmn, 42c0, eb100f00), \
X(cmp, 2800, ebb00f00), \
X(cpsie, b660, f3af8400), \
@@ -5869,7 +5854,6 @@ static void
do_t_adr (void)
{
inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
- inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
inst.reloc.pc_rel = 1;
inst.instruction |= inst.operands[0].reg << 4;
@@ -6096,7 +6080,7 @@ do_t_blx (void)
else
{
/* No register. This must be BLX(1). */
- inst.instruction = 0xf7ffeffe;
+ inst.instruction = 0xf700e800;
inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX;
inst.reloc.pc_rel = 1;
}
@@ -6109,7 +6093,7 @@ do_t_branch (void)
{
if (inst.instruction == T_OPCODE_BRANCH)
{
- inst.instruction = 0xf7ffbffe;
+ inst.instruction = 0xf000b800;
inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25;
}
else
@@ -6117,7 +6101,7 @@ do_t_branch (void)
int cond = inst.instruction & 0x0f00;
constraint (cond == 0xE00 || cond == 0xF00,
_("invalid condition for wide conditional branch"));
- inst.instruction = (cond << 14) | 0xf43faffe;
+ inst.instruction = (cond << 14) | 0xf0008000;
inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20;
}
}
@@ -6454,8 +6438,6 @@ do_t_ldst (void)
inst.instruction |= inst.operands[0].reg << 8;
inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
- if (inst.reloc.pc_rel)
- inst.reloc.exp.X_add_number -= 4; /* pipeline offset */
return;
}
@@ -7873,15 +7855,9 @@ static const struct asm_opcode insns[] =
tCM(ldm,ia, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
tCM(ldm,fd, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
- TCE(swi, f000000, df00, 1, (EXPi), swi, t_swi),
-#ifdef TE_WINCE
- /* XXX This is the wrong place to do this. Think multi-arch. */
- TCC(b, a000000, e7fe, d,fe, 1, (EXPr), branch, t_branch),
- TCE(bl, b000000, f7fffffe, 1, (EXPr), branch, t_branch23),
-#else
- TCC(b, afffffe, e7fe, d,fe, 1, (EXPr), branch, t_branch),
- TCE(bl, bfffffe, f7fffffe, 1, (EXPr), branch, t_branch23),
-#endif
+ TCE(swi, f000000, df00, 1, (EXPi), swi, t_swi),
+ TCC(b, a000000, e000, d,00, 1, (EXPr), branch, t_branch),
+ TCE(bl, b000000, f000f800, 1, (EXPr), branch, t_branch23),
/* Pseudo ops. */
TCE(adr, 28f0000, 000f, 2, (RR, EXP), adr, t_adr),
@@ -9652,33 +9628,31 @@ tc_arm_frame_initial_instructions (void)
/* MD interface: Symbol and relocation handling. */
-
-/* The knowledge of the PC's pipeline offset is built into the insns
- themselves. */
-
long
md_pcrel_from (fixS * fixP)
{
+ /* The pipeline offset is 4 for Thumb instructions, 8 for ARM. */
if (fixP->fx_addsy
&& S_GET_SEGMENT (fixP->fx_addsy) == undefined_section
&& fixP->fx_subsy == NULL)
- return 0;
+ return fixP->tc_fix_data ? 4 : 8;
- if (fixP->fx_pcrel && (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_ADD))
+ if (!fixP->tc_fix_data) /* ARM */
+ return fixP->fx_where + fixP->fx_frag->fr_address + 8;
+
+ /* PC relative load/store - not branches - on Thumb forces the
+ bottom two bits of the PC to zero. */
+
+ switch (fixP->fx_r_type)
{
- /* PC relative addressing on the Thumb is slightly odd
- as the bottom two bits of the PC are forced to zero
- for the calculation. */
- return (fixP->fx_where + fixP->fx_frag->fr_address) & ~3;
- }
+ case BFD_RELOC_ARM_THUMB_ADD:
+ case BFD_RELOC_ARM_THUMB_OFFSET:
+ case BFD_RELOC_ARM_T32_OFFSET_IMM:
+ return ((fixP->fx_where + fixP->fx_frag->fr_address) & ~3) + 4;
-#ifdef TE_WINCE
- /* The pattern was adjusted to accommodate CE's off-by-one fixups,
- so we un-adjust here to compensate for the accommodation. */
- return fixP->fx_where + fixP->fx_frag->fr_address + 8;
-#else
- return fixP->fx_where + fixP->fx_frag->fr_address;
-#endif
+ default:
+ return fixP->fx_where + fixP->fx_frag->fr_address + 4;
+ }
}
/* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
@@ -9858,23 +9832,10 @@ md_apply_fix3 (fixS * fixP,
to an integer of different size. We know the value is 0, 1, or 2. */
int fix_is_thumb = (int) (size_t) fixP->tc_fix_data;
- assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
-
/* Note whether this will delete the relocation. */
if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
fixP->fx_done = 1;
- /* If this symbol is in a different section then we need to leave it for
- the linker to deal with. Unfortunately, md_pcrel_from can't tell,
- so we have to undo it's effects here. */
- if (fixP->fx_pcrel)
- {
- if (fixP->fx_addsy != NULL
- && S_IS_DEFINED (fixP->fx_addsy)
- && S_GET_SEGMENT (fixP->fx_addsy) != seg)
- value += md_pcrel_from (fixP);
- }
-
/* Remember value for emit_reloc. */
fixP->fx_addnumber = value;
@@ -10073,7 +10034,7 @@ md_apply_fix3 (fixS * fixP,
}
newval &= ~0xff;
}
- else if ((newval & 0x0000f000) == 0x0000f0000)
+ else if ((newval & 0x000f0000) == 0x000f0000)
{
/* PC-relative, 12-bit offset. */
if (value >= 0)
@@ -10086,7 +10047,7 @@ md_apply_fix3 (fixS * fixP,
_("offset out of range"));
break;
}
- newval &= ~0xfff;
+ newval &= ~0xfff; /* clear secondary opcode */
}
else if ((newval & 0x00000100) == 0x00000100)
{
@@ -10248,7 +10209,7 @@ md_apply_fix3 (fixS * fixP,
#define SEXT24(x) ((((x) & 0xffffff) ^ (~ 0x7fffff)) + 0x800000)
#ifdef OBJ_ELF
- value = fixP->fx_offset;
+ value = fixP->fx_offset - 8;
#endif
/* We are going to store value (shifted right by two) in the
@@ -10318,7 +10279,7 @@ md_apply_fix3 (fixS * fixP,
newval = md_chars_to_number (buf, INSN_SIZE);
#ifdef OBJ_ELF
- value = fixP->fx_offset;
+ value = fixP->fx_offset - 8;
#endif
hbit = (value >> 1) & 1;
value = (value >> 2) & 0x00ffffff;
@@ -10345,9 +10306,6 @@ md_apply_fix3 (fixS * fixP,
case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CZB */
newval = md_chars_to_number (buf, THUMB_SIZE);
{
- addressT diff = ((newval & 0x00f8) >> 2) | (newval & 0x0200) >> 3;
- /* This one does not have the offset encoded in the pattern. */
- value = value + diff - 4;
/* CZB can only branch forward. */
if (value & ~0x7e)
as_bad_where (fixP->fx_file, fixP->fx_line,
@@ -10370,11 +10328,6 @@ md_apply_fix3 (fixS * fixP,
case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
newval = md_chars_to_number (buf, THUMB_SIZE);
{
- addressT diff = (newval & 0xff) << 1;
- if (diff & 0x100)
- diff |= ~0xff;
-
- value += diff;
if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
as_bad_where (fixP->fx_file, fixP->fx_line,
_("branch out of range"));
@@ -10395,11 +10348,6 @@ md_apply_fix3 (fixS * fixP,
case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
newval = md_chars_to_number (buf, THUMB_SIZE);
{
- addressT diff = (newval & 0x7ff) << 1;
- if (diff & 0x800)
- diff |= ~0x7ff;
-
- value += diff;
if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
as_bad_where (fixP->fx_file, fixP->fx_line,
_("branch out of range"));
@@ -10420,21 +10368,10 @@ md_apply_fix3 (fixS * fixP,
case BFD_RELOC_THUMB_PCREL_BRANCH20:
{
offsetT newval2;
- addressT diff, S, J1, J2, lo, hi;
newval = md_chars_to_number (buf, THUMB_SIZE);
newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
- S = !(newval & 0x0400); /* flipped - 0=negative */
- hi = (newval & 0x003f);
- J1 = (newval2 & 0x2000) >> 13;
- J2 = (newval2 & 0x0800) >> 11;
- lo = (newval2 & 0x07ff);
-
- diff = ((S << 20) | (J2 << 19) | (J1 << 18) | (hi << 12) | (lo << 1));
- diff -= (1 << 20); /* sign extend */
- value += diff;
-
if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff))
as_bad_where (fixP->fx_file, fixP->fx_line,
_("conditional branch out of range"));
@@ -10450,6 +10387,7 @@ md_apply_fix3 (fixS * fixP,
}
else
{
+ addressT S, J1, J2, lo, hi;
S = (value & 0x00100000) >> 20;
J2 = (value & 0x00080000) >> 19;
J1 = (value & 0x00040000) >> 18;
@@ -10469,17 +10407,13 @@ md_apply_fix3 (fixS * fixP,
case BFD_RELOC_THUMB_PCREL_BRANCH23:
{
offsetT newval2;
- addressT diff;
newval = md_chars_to_number (buf, THUMB_SIZE);
newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
- diff = ((newval & 0x7ff) << 12) | ((newval2 & 0x7ff) << 1);
- if (diff & 0x400000)
- diff |= ~0x3fffff;
+
#ifdef OBJ_ELF
- value = fixP->fx_offset;
+ value = fixP->fx_offset - 4;
#endif
- value += diff;
if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
as_bad_where (fixP->fx_file, fixP->fx_line,
@@ -10528,25 +10462,10 @@ md_apply_fix3 (fixS * fixP,
case BFD_RELOC_THUMB_PCREL_BRANCH25:
{
offsetT newval2;
- addressT diff, S, I1, I2, lo, hi;
newval = md_chars_to_number (buf, THUMB_SIZE);
newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
- S = (newval & 0x0400) >> 10;
- hi = (newval & 0x03ff);
- I1 = (newval2 & 0x2000) >> 13;
- I2 = (newval2 & 0x0800) >> 11;
- lo = (newval2 & 0x07ff);
-
- I1 = !(I1 ^ S);
- I2 = !(I2 ^ S);
- S = !S;
-
- diff = ((S << 24) | (I1 << 23) | (I2 << 22) | (hi << 12) | (lo << 1));
- diff -= (1 << 24); /* sign extend */
- value += diff;
-
if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff))
as_bad_where (fixP->fx_file, fixP->fx_line,
_("branch out of range"));
@@ -10562,6 +10481,7 @@ md_apply_fix3 (fixS * fixP,
}
else
{
+ addressT S, I1, I2, lo, hi;
S = (value & 0x01000000) >> 24;
I1 = (value & 0x00800000) >> 23;
I2 = (value & 0x00400000) >> 22;
===================================================================
Index: opcodes/arm-dis.c
--- opcodes/arm-dis.c (revision 84)
+++ opcodes/arm-dis.c (working copy)
@@ -1,4 +1,4 @@
-/* Instruction printing code for the ARM
+/* Instruction pritning code for the ARM
Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
Free Software Foundation, Inc.
Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
@@ -2278,61 +2278,75 @@ print_insn_thumb32 (pc, info, given)
unsigned int op = (given & 0x00000f00) >> 8;
unsigned int i12 = (given & 0x00000fff);
unsigned int i8 = (given & 0x000000ff);
+ bfd_boolean writeback = FALSE, postind = FALSE;
+ int offset = 0;
func (stream, "[%s", arm_regnames[Rn]);
if (U) /* 12-bit positive immediate offset */
+ offset = i12;
+ else if (Rn == 15) /* 12-bit negative immediate offset */
+ offset = -(int)i12;
+ else if (op == 0x0) /* shifted register offset */
{
- if (i12)
- func (stream, ", #%u", i12);
+ unsigned int Rm = (i8 & 0x0f);
+ unsigned int sh = (i8 & 0x30) >> 4;
+ func (stream, ", %s", arm_regnames[Rm]);
+ if (sh)
+ func (stream, ", lsl #%u", sh);
func (stream, "]");
+ break;
}
- else if (Rn == 15) /* 12-bit negative immediate offset */
- func (stream, ", #-%u]", i12);
else switch (op)
{
- case 0x0: /* shifted register offset */
- {
- unsigned int Rm = (i8 & 0x0f);
- unsigned int sh = (i8 & 0x30) >> 4;
- func (stream, ", %s", arm_regnames[Rm]);
- if (sh)
- func (stream, ", lsl #%u", sh);
- func (stream, "]");
- }
- break;
-
case 0xE: /* 8-bit positive immediate offset */
- if (i8)
- func (stream, ", #%u", i8);
- func (stream, "]");
+ offset = i8;
break;
case 0xC: /* 8-bit negative immediate offset */
- func (stream, ", #-%u]", i8);
+ offset = -i8;
break;
case 0xB: /* 8-bit + preindex with wb */
- if (i8)
- func (stream, ", #%u", i8);
- func (stream, "]!");
+ offset = i8;
+ writeback = TRUE;
break;
case 0x9: /* 8-bit - preindex with wb */
- func (stream, ", #-%u]!", i8);
+ offset = -i8;
+ writeback = TRUE;
break;
case 0xF: /* 8-bit + postindex */
- func (stream, "], #%u", i8);
+ offset = i8;
+ postind = TRUE;
break;
case 0xD: /* 8-bit - postindex */
- func (stream, "], #-%u", i8);
+ offset = -i8;
+ postind = TRUE;
break;
default:
func (stream, ", <undefined>]");
+ goto skip;
+ }
+
+ if (postind)
+ func (stream, "], #%d", offset);
+ else
+ {
+ if (offset)
+ func (stream, ", #%d", offset);
+ func (stream, writeback ? "]!" : "]");
+ }
+
+ if (Rn == 15)
+ {
+ func (stream, "\t; ");
+ info->print_address_func (((pc + 4) & ~3) + offset, info);
}
}
+ skip:
break;
case 'A':
@@ -2425,7 +2439,7 @@ print_insn_thumb32 (pc, info, given)
unsigned int S = (given & 0x04000000u) >> 26;
unsigned int J1 = (given & 0x00002000u) >> 13;
unsigned int J2 = (given & 0x00000800u) >> 11;
- unsigned int offset = 0;
+ int offset = 0;
offset |= !S << 20;
offset |= J2 << 19;
@@ -2434,7 +2448,7 @@ print_insn_thumb32 (pc, info, given)
offset |= (given & 0x000007ff) << 1;
offset -= (1 << 20);
- info->print_address_func ((bfd_vma)offset + pc + 4, info);
+ info->print_address_func (pc + 4 + offset, info);
}
break;
@@ -2443,7 +2457,7 @@ print_insn_thumb32 (pc, info, given)
unsigned int S = (given & 0x04000000u) >> 26;
unsigned int I1 = (given & 0x00002000u) >> 13;
unsigned int I2 = (given & 0x00000800u) >> 11;
- unsigned int offset = 0;
+ int offset = 0;
offset |= !S << 24;
offset |= !(I1 ^ S) << 23;
@@ -2452,7 +2466,7 @@ print_insn_thumb32 (pc, info, given)
offset |= (given & 0x000007ffu) << 1;
offset -= (1 << 24);
- info->print_address_func ((bfd_vma)offset + pc + 4, info);
+ info->print_address_func (pc + 4 + offset, info);
}
break;
===================================================================
Index: gas/testsuite/gas/arm/pic.d
--- gas/testsuite/gas/arm/pic.d (revision 84)
+++ gas/testsuite/gas/arm/pic.d (working copy)
@@ -6,9 +6,9 @@
.*: +file format .*arm.*
Disassembly of section .text:
-00+0 <[^>]*> eb...... bl 00+. <[^>]*>
- 0: R_ARM_PC24 foo.*
-00+4 <[^>]*> ebfffffe bl 0[0123456789abcdef]+ <[^>]*>
+0+0 <[^>]*> ebfffffe bl 0+0 <[^>]*>
+ 0: R_ARM_PC24 foo
+0+4 <[^>]*> eb000000 bl 0+8 <[^>]*>
4: R_ARM_PLT32 foo
\.\.\.
8: R_ARM_ABS32 sym
===================================================================
Index: gas/testsuite/gas/arm/thumb32.d
--- gas/testsuite/gas/arm/thumb32.d (revision 84)
+++ gas/testsuite/gas/arm/thumb32.d (working copy)
@@ -209,100 +209,100 @@ Disassembly of section .text:
0+2ce <[^>]+> f3c0 5040 ubfx r0, r0, #21, #1
0+2d2 <[^>]+> f340 0011 sbfx r0, r0, #0, #18
0+2d6 <[^>]+> d0fe beq\.n 0+2d6 <[^>]+>
-0+2d8 <[^>]+> d029 beq\.n 0+32e <[^>]+>
+0+2d8 <[^>]+> d02a beq\.n 0+330 <[^>]+>
0+2da <[^>]+> d1fc bne\.n 0+2d6 <[^>]+>
-0+2dc <[^>]+> d127 bne\.n 0+32e <[^>]+>
+0+2dc <[^>]+> d128 bne\.n 0+330 <[^>]+>
0+2de <[^>]+> d2fa bcs\.n 0+2d6 <[^>]+>
-0+2e0 <[^>]+> d225 bcs\.n 0+32e <[^>]+>
+0+2e0 <[^>]+> d226 bcs\.n 0+330 <[^>]+>
0+2e2 <[^>]+> d2f8 bcs\.n 0+2d6 <[^>]+>
-0+2e4 <[^>]+> d223 bcs\.n 0+32e <[^>]+>
+0+2e4 <[^>]+> d224 bcs\.n 0+330 <[^>]+>
0+2e6 <[^>]+> d3f6 bcc\.n 0+2d6 <[^>]+>
-0+2e8 <[^>]+> d321 bcc\.n 0+32e <[^>]+>
+0+2e8 <[^>]+> d322 bcc\.n 0+330 <[^>]+>
0+2ea <[^>]+> d3f4 bcc\.n 0+2d6 <[^>]+>
-0+2ec <[^>]+> d31f bcc\.n 0+32e <[^>]+>
+0+2ec <[^>]+> d320 bcc\.n 0+330 <[^>]+>
0+2ee <[^>]+> d3f2 bcc\.n 0+2d6 <[^>]+>
-0+2f0 <[^>]+> d31d bcc\.n 0+32e <[^>]+>
+0+2f0 <[^>]+> d31e bcc\.n 0+330 <[^>]+>
0+2f2 <[^>]+> d4f0 bmi\.n 0+2d6 <[^>]+>
-0+2f4 <[^>]+> d41b bmi\.n 0+32e <[^>]+>
+0+2f4 <[^>]+> d41c bmi\.n 0+330 <[^>]+>
0+2f6 <[^>]+> d5ee bpl\.n 0+2d6 <[^>]+>
-0+2f8 <[^>]+> d519 bpl\.n 0+32e <[^>]+>
+0+2f8 <[^>]+> d51a bpl\.n 0+330 <[^>]+>
0+2fa <[^>]+> d6ec bvs\.n 0+2d6 <[^>]+>
-0+2fc <[^>]+> d617 bvs\.n 0+32e <[^>]+>
+0+2fc <[^>]+> d618 bvs\.n 0+330 <[^>]+>
0+2fe <[^>]+> d7ea bvc\.n 0+2d6 <[^>]+>
-0+300 <[^>]+> d715 bvc\.n 0+32e <[^>]+>
+0+300 <[^>]+> d716 bvc\.n 0+330 <[^>]+>
0+302 <[^>]+> d8e8 bhi\.n 0+2d6 <[^>]+>
-0+304 <[^>]+> d813 bhi\.n 0+32e <[^>]+>
+0+304 <[^>]+> d814 bhi\.n 0+330 <[^>]+>
0+306 <[^>]+> d9e6 bls\.n 0+2d6 <[^>]+>
-0+308 <[^>]+> d911 bls\.n 0+32e <[^>]+>
+0+308 <[^>]+> d912 bls\.n 0+330 <[^>]+>
0+30a <[^>]+> d7e4 bvc\.n 0+2d6 <[^>]+>
-0+30c <[^>]+> d70f bvc\.n 0+32e <[^>]+>
+0+30c <[^>]+> d710 bvc\.n 0+330 <[^>]+>
0+30e <[^>]+> d8e2 bhi\.n 0+2d6 <[^>]+>
-0+310 <[^>]+> d80d bhi\.n 0+32e <[^>]+>
+0+310 <[^>]+> d80e bhi\.n 0+330 <[^>]+>
0+312 <[^>]+> d9e0 bls\.n 0+2d6 <[^>]+>
-0+314 <[^>]+> d90b bls\.n 0+32e <[^>]+>
+0+314 <[^>]+> d90c bls\.n 0+330 <[^>]+>
0+316 <[^>]+> dade bge\.n 0+2d6 <[^>]+>
-0+318 <[^>]+> da09 bge\.n 0+32e <[^>]+>
+0+318 <[^>]+> da0a bge\.n 0+330 <[^>]+>
0+31a <[^>]+> dbdc blt\.n 0+2d6 <[^>]+>
-0+31c <[^>]+> db07 blt\.n 0+32e <[^>]+>
+0+31c <[^>]+> db08 blt\.n 0+330 <[^>]+>
0+31e <[^>]+> dcda bgt\.n 0+2d6 <[^>]+>
-0+320 <[^>]+> dc05 bgt\.n 0+32e <[^>]+>
+0+320 <[^>]+> dc06 bgt\.n 0+330 <[^>]+>
0+322 <[^>]+> ddd8 ble\.n 0+2d6 <[^>]+>
-0+324 <[^>]+> dd03 ble\.n 0+32e <[^>]+>
+0+324 <[^>]+> dd04 ble\.n 0+330 <[^>]+>
0+326 <[^>]+> ded6 bal\.n 0+2d6 <[^>]+>
-0+328 <[^>]+> de01 bal\.n 0+32e <[^>]+>
+0+328 <[^>]+> de02 bal\.n 0+330 <[^>]+>
0+32a <[^>]+> e7d4 b\.n 0+2d6 <[^>]+>
-0+32c <[^>]+> e7ff b\.n 0+32e <[^>]+>
-0+32e <[^>]+> f43f affe beq\.w 0+32e <[^>]+>
-0+332 <[^>]+> f000 8058 beq\.w 0+3e6 <[^>]+>
-0+336 <[^>]+> f47f affa bne\.w 0+32e <[^>]+>
-0+33a <[^>]+> f040 8054 bne\.w 0+3e6 <[^>]+>
-0+33e <[^>]+> f4bf aff6 bcs\.w 0+32e <[^>]+>
-0+342 <[^>]+> f080 8050 bcs\.w 0+3e6 <[^>]+>
-0+346 <[^>]+> f4bf aff2 bcs\.w 0+32e <[^>]+>
-0+34a <[^>]+> f080 804c bcs\.w 0+3e6 <[^>]+>
-0+34e <[^>]+> f4ff afee bcc\.w 0+32e <[^>]+>
-0+352 <[^>]+> f0c0 8048 bcc\.w 0+3e6 <[^>]+>
-0+356 <[^>]+> f4ff afea bcc\.w 0+32e <[^>]+>
-0+35a <[^>]+> f0c0 8044 bcc\.w 0+3e6 <[^>]+>
-0+35e <[^>]+> f4ff afe6 bcc\.w 0+32e <[^>]+>
-0+362 <[^>]+> f0c0 8040 bcc\.w 0+3e6 <[^>]+>
-0+366 <[^>]+> f53f afe2 bmi\.w 0+32e <[^>]+>
-0+36a <[^>]+> f100 803c bmi\.w 0+3e6 <[^>]+>
-0+36e <[^>]+> f57f afde bpl\.w 0+32e <[^>]+>
-0+372 <[^>]+> f140 8038 bpl\.w 0+3e6 <[^>]+>
-0+376 <[^>]+> f5bf afda bvs\.w 0+32e <[^>]+>
-0+37a <[^>]+> f180 8034 bvs\.w 0+3e6 <[^>]+>
-0+37e <[^>]+> f5ff afd6 bvc\.w 0+32e <[^>]+>
-0+382 <[^>]+> f1c0 8030 bvc\.w 0+3e6 <[^>]+>
-0+386 <[^>]+> f63f afd2 bhi\.w 0+32e <[^>]+>
-0+38a <[^>]+> f200 802c bhi\.w 0+3e6 <[^>]+>
-0+38e <[^>]+> f67f afce bls\.w 0+32e <[^>]+>
-0+392 <[^>]+> f240 8028 bls\.w 0+3e6 <[^>]+>
-0+396 <[^>]+> f5ff afca bvc\.w 0+32e <[^>]+>
-0+39a <[^>]+> f1c0 8024 bvc\.w 0+3e6 <[^>]+>
-0+39e <[^>]+> f63f afc6 bhi\.w 0+32e <[^>]+>
-0+3a2 <[^>]+> f200 8020 bhi\.w 0+3e6 <[^>]+>
-0+3a6 <[^>]+> f67f afc2 bls\.w 0+32e <[^>]+>
-0+3aa <[^>]+> f240 801c bls\.w 0+3e6 <[^>]+>
-0+3ae <[^>]+> f6bf afbe bge\.w 0+32e <[^>]+>
-0+3b2 <[^>]+> f280 8018 bge\.w 0+3e6 <[^>]+>
-0+3b6 <[^>]+> f6ff afba blt\.w 0+32e <[^>]+>
-0+3ba <[^>]+> f2c0 8014 blt\.w 0+3e6 <[^>]+>
-0+3be <[^>]+> f73f afb6 bgt\.w 0+32e <[^>]+>
-0+3c2 <[^>]+> f300 8010 bgt\.w 0+3e6 <[^>]+>
-0+3c6 <[^>]+> f77f afb2 ble\.w 0+32e <[^>]+>
-0+3ca <[^>]+> f340 800c ble\.w 0+3e6 <[^>]+>
-0+3ce <[^>]+> f7ff bfae b\.w 0+32e <[^>]+>
-0+3d2 <[^>]+> f000 b808 b\.w 0+3e6 <[^>]+>
-0+3d6 <[^>]+> f000 f995 bl 0+32e <[^>]+>
- 3d6: R_ARM_THM_CALL \.text
-0+3da <[^>]+> f000 f9f1 bl 0+3e6 <[^>]+>
- 3da: R_ARM_THM_CALL \.text
-0+3de <[^>]+> f000 e995 blx 0+32e <[^>]+>
- 3de: R_ARM_THM_XPC22 \.text
-0+3e2 <[^>]+> f000 e9f1 blx 0+3e6 <[^>]+>
- 3e2: R_ARM_THM_XPC22 \.text
-0+3e6 <[^>]+> 4700 bx r0
+0+32c <[^>]+> e000 b\.n 0+330 <[^>]+>
+0+32e <[^>]+> 46c0 nop \(mov r8, r8\)
+0+330 <[^>]+> f43f affe beq\.w 0+330 <[^>]+>
+0+334 <[^>]+> f000 8058 beq\.w 0+3e8 <[^>]+>
+0+338 <[^>]+> f47f affa bne\.w 0+330 <[^>]+>
+0+33c <[^>]+> f040 8054 bne\.w 0+3e8 <[^>]+>
+0+340 <[^>]+> f4bf aff6 bcs\.w 0+330 <[^>]+>
+0+344 <[^>]+> f080 8050 bcs\.w 0+3e8 <[^>]+>
+0+348 <[^>]+> f4bf aff2 bcs\.w 0+330 <[^>]+>
+0+34c <[^>]+> f080 804c bcs\.w 0+3e8 <[^>]+>
+0+350 <[^>]+> f4ff afee bcc\.w 0+330 <[^>]+>
+0+354 <[^>]+> f0c0 8048 bcc\.w 0+3e8 <[^>]+>
+0+358 <[^>]+> f4ff afea bcc\.w 0+330 <[^>]+>
+0+35c <[^>]+> f0c0 8044 bcc\.w 0+3e8 <[^>]+>
+0+360 <[^>]+> f4ff afe6 bcc\.w 0+330 <[^>]+>
+0+364 <[^>]+> f0c0 8040 bcc\.w 0+3e8 <[^>]+>
+0+368 <[^>]+> f53f afe2 bmi\.w 0+330 <[^>]+>
+0+36c <[^>]+> f100 803c bmi\.w 0+3e8 <[^>]+>
+0+370 <[^>]+> f57f afde bpl\.w 0+330 <[^>]+>
+0+374 <[^>]+> f140 8038 bpl\.w 0+3e8 <[^>]+>
+0+378 <[^>]+> f5bf afda bvs\.w 0+330 <[^>]+>
+0+37c <[^>]+> f180 8034 bvs\.w 0+3e8 <[^>]+>
+0+380 <[^>]+> f5ff afd6 bvc\.w 0+330 <[^>]+>
+0+384 <[^>]+> f1c0 8030 bvc\.w 0+3e8 <[^>]+>
+0+388 <[^>]+> f63f afd2 bhi\.w 0+330 <[^>]+>
+0+38c <[^>]+> f200 802c bhi\.w 0+3e8 <[^>]+>
+0+390 <[^>]+> f67f afce bls\.w 0+330 <[^>]+>
+0+394 <[^>]+> f240 8028 bls\.w 0+3e8 <[^>]+>
+0+398 <[^>]+> f5ff afca bvc\.w 0+330 <[^>]+>
+0+39c <[^>]+> f1c0 8024 bvc\.w 0+3e8 <[^>]+>
+0+3a0 <[^>]+> f63f afc6 bhi\.w 0+330 <[^>]+>
+0+3a4 <[^>]+> f200 8020 bhi\.w 0+3e8 <[^>]+>
+0+3a8 <[^>]+> f67f afc2 bls\.w 0+330 <[^>]+>
+0+3ac <[^>]+> f240 801c bls\.w 0+3e8 <[^>]+>
+0+3b0 <[^>]+> f6bf afbe bge\.w 0+330 <[^>]+>
+0+3b4 <[^>]+> f280 8018 bge\.w 0+3e8 <[^>]+>
+0+3b8 <[^>]+> f6ff afba blt\.w 0+330 <[^>]+>
+0+3bc <[^>]+> f2c0 8014 blt\.w 0+3e8 <[^>]+>
+0+3c0 <[^>]+> f73f afb6 bgt\.w 0+330 <[^>]+>
+0+3c4 <[^>]+> f300 8010 bgt\.w 0+3e8 <[^>]+>
+0+3c8 <[^>]+> f77f afb2 ble\.w 0+330 <[^>]+>
+0+3cc <[^>]+> f340 800c ble\.w 0+3e8 <[^>]+>
+0+3d0 <[^>]+> f7ff bfae b\.w 0+330 <[^>]+>
+0+3d4 <[^>]+> f000 b808 b\.w 0+3e8 <[^>]+>
+0+3d8 <[^>]+> f000 f996 bl 0+330 <[^>]+>
+ 3d8: R_ARM_THM_CALL \.text
+0+3dc <[^>]+> f000 f9f2 bl 0+3e8 <[^>]+>
+ 3dc: R_ARM_THM_CALL \.text
+0+3e0 <[^>]+> f000 e996 blx 0+330 <[^>]+>
+ 3e0: R_ARM_THM_XPC22 \.text
+0+3e4 <[^>]+> f000 e9f2 blx 0+3e8 <[^>]+>
+ 3e4: R_ARM_THM_XPC22 \.text
0+3e8 <[^>]+> 4748 bx r9
0+3ea <[^>]+> 4780 blx r0
0+3ec <[^>]+> 47c8 blx r9
@@ -508,8 +508,8 @@ Disassembly of section .text:
0+5b2 <[^>]+> f815 1d30 ldrb\.w r1, \[r5\], #-48
0+5b6 <[^>]+> 5d29 ldrb r1, \[r5, r4\]
0+5b8 <[^>]+> f819 100c ldrb\.w r1, \[r9, ip\]
-0+5bc <[^>]+> f89f 10b0 ldrb\.w r1, \[pc, #176\]
-0+5c0 <[^>]+> f81f 1c26 ldrb\.w r1, \[pc, #-3110\]
+0+5bc <[^>]+> f89f 10ac ldrb\.w r1, \[pc, #172\] ; 0+66c <[^>]+>
+0+5c0 <[^>]+> f81f 102a ldrb\.w r1, \[pc, #-42\] ; 0+59a <[^>]+>
0+5c4 <[^>]+> f995 1000 ldrsb\.w r1, \[r5\]
0+5c8 <[^>]+> f995 1330 ldrsb\.w r1, \[r5, #816\]
0+5cc <[^>]+> f915 1c30 ldrsb\.w r1, \[r5, #-48\]
@@ -519,8 +519,8 @@ Disassembly of section .text:
0+5dc <[^>]+> f915 1d30 ldrsb\.w r1, \[r5\], #-48
0+5e0 <[^>]+> 5729 ldrsb r1, \[r5, r4\]
0+5e2 <[^>]+> f919 100c ldrsb\.w r1, \[r9, ip\]
-0+5e6 <[^>]+> f99f 1086 ldrsb\.w r1, \[pc, #134\]
-0+5ea <[^>]+> f91f 1c50 ldrsb\.w r1, \[pc, #-3152\]
+0+5e6 <[^>]+> f99f 1084 ldrsb\.w r1, \[pc, #132\] ; 0+66c <[^>]+>
+0+5ea <[^>]+> f91f 1052 ldrsb\.w r1, \[pc, #-82\] ; 0+59a <[^>]+>
0+5ee <[^>]+> f8b5 1000 ldrh\.w r1, \[r5\]
0+5f2 <[^>]+> f8b5 1330 ldrh\.w r1, \[r5, #816\]
0+5f6 <[^>]+> f835 1c30 ldrh\.w r1, \[r5, #-48\]
@@ -530,8 +530,8 @@ Disassembly of section .text:
0+606 <[^>]+> f835 1d30 ldrh\.w r1, \[r5\], #-48
0+60a <[^>]+> 5b29 ldrh r1, \[r5, r4\]
0+60c <[^>]+> f839 100c ldrh\.w r1, \[r9, ip\]
-0+610 <[^>]+> f8bf 105c ldrh\.w r1, \[pc, #92\]
-0+614 <[^>]+> f83f 1c7a ldrh\.w r1, \[pc, #-3194\]
+0+610 <[^>]+> f8bf 1058 ldrh\.w r1, \[pc, #88\] ; 0+66c <[^>]+>
+0+614 <[^>]+> f83f 107e ldrh\.w r1, \[pc, #-126\] ; 0+59a <[^>]+>
0+618 <[^>]+> f9b5 1000 ldrsh\.w r1, \[r5\]
0+61c <[^>]+> f9b5 1330 ldrsh\.w r1, \[r5, #816\]
0+620 <[^>]+> f935 1c30 ldrsh\.w r1, \[r5, #-48\]
@@ -541,8 +541,8 @@ Disassembly of section .text:
0+630 <[^>]+> f935 1d30 ldrsh\.w r1, \[r5\], #-48
0+634 <[^>]+> 5f29 ldrsh r1, \[r5, r4\]
0+636 <[^>]+> f939 100c ldrsh\.w r1, \[r9, ip\]
-0+63a <[^>]+> f9bf 1032 ldrsh\.w r1, \[pc, #50\]
-0+63e <[^>]+> f93f 1ca4 ldrsh\.w r1, \[pc, #-3236\]
+0+63a <[^>]+> f9bf 1030 ldrsh\.w r1, \[pc, #48\] ; 0+66c <[^>]+>
+0+63e <[^>]+> f93f 10a6 ldrsh\.w r1, \[pc, #-166\] ; 0+59a <[^>]+>
0+642 <[^>]+> f8d5 1000 ldr\.w r1, \[r5\]
0+646 <[^>]+> f8d5 1330 ldr\.w r1, \[r5, #816\]
0+64a <[^>]+> f855 1c30 ldr\.w r1, \[r5, #-48\]
@@ -552,8 +552,8 @@ Disassembly of section .text:
0+65a <[^>]+> f855 1d30 ldr\.w r1, \[r5\], #-48
0+65e <[^>]+> 5929 ldr r1, \[r5, r4\]
0+660 <[^>]+> f859 100c ldr\.w r1, \[r9, ip\]
-0+664 <[^>]+> f8df 1008 ldr\.w r1, \[pc, #8\]
-0+668 <[^>]+> f85f 1cce ldr\.w r1, \[pc, #-3278\]
+0+664 <[^>]+> f8df 1004 ldr\.w r1, \[pc, #4\] ; 0+66c <[^>]+>
+0+668 <[^>]+> f85f 10d2 ldr\.w r1, \[pc, #-210\] ; 0+59a <[^>]+>
0+66c <[^>]+> f885 1000 strb\.w r1, \[r5\]
0+670 <[^>]+> f885 1330 strb\.w r1, \[r5, #816\]
0+674 <[^>]+> f805 1c30 strb\.w r1, \[r5, #-48\]
@@ -563,8 +563,8 @@ Disassembly of section .text:
0+684 <[^>]+> f805 1d30 strb\.w r1, \[r5\], #-48
0+688 <[^>]+> 5529 strb r1, \[r5, r4\]
0+68a <[^>]+> f809 100c strb\.w r1, \[r9, ip\]
-0+68e <[^>]+> f88f 1088 strb\.w r1, \[pc, #136\]
-0+692 <[^>]+> f80f 1c26 strb\.w r1, \[pc, #-3110\]
+0+68e <[^>]+> f88f 1086 strb\.w r1, \[pc, #134\] ; 0+716 <[^>]+>
+0+692 <[^>]+> f80f 1028 strb\.w r1, \[pc, #-40\] ; 0+66c <[^>]+>
0+696 <[^>]+> f8a5 1000 strh\.w r1, \[r5\]
0+69a <[^>]+> f8a5 1330 strh\.w r1, \[r5, #816\]
0+69e <[^>]+> f825 1c30 strh\.w r1, \[r5, #-48\]
@@ -574,8 +574,8 @@ Disassembly of section .text:
0+6ae <[^>]+> f825 1d30 strh\.w r1, \[r5\], #-48
0+6b2 <[^>]+> 5329 strh r1, \[r5, r4\]
0+6b4 <[^>]+> f829 100c strh\.w r1, \[r9, ip\]
-0+6b8 <[^>]+> f8af 105e strh\.w r1, \[pc, #94\]
-0+6bc <[^>]+> f82f 1c50 strh\.w r1, \[pc, #-3152\]
+0+6b8 <[^>]+> f8af 105a strh\.w r1, \[pc, #90\] ; 0+716 <[^>]+>
+0+6bc <[^>]+> f82f 1054 strh\.w r1, \[pc, #-84\] ; 0+66c <[^>]+>
0+6c0 <[^>]+> f8c5 1000 str\.w r1, \[r5\]
0+6c4 <[^>]+> f8c5 1330 str\.w r1, \[r5, #816\]
0+6c8 <[^>]+> f845 1c30 str\.w r1, \[r5, #-48\]
@@ -585,8 +585,8 @@ Disassembly of section .text:
0+6d8 <[^>]+> f845 1d30 str\.w r1, \[r5\], #-48
0+6dc <[^>]+> 5129 str r1, \[r5, r4\]
0+6de <[^>]+> f849 100c str\.w r1, \[r9, ip\]
-0+6e2 <[^>]+> f8cf 1034 str\.w r1, \[pc, #52\]
-0+6e6 <[^>]+> f84f 1c7a str\.w r1, \[pc, #-3194\]
+0+6e2 <[^>]+> f8cf 1032 str\.w r1, \[pc, #50\] ; 0+716 <[^>]+>
+0+6e6 <[^>]+> f84f 107c str\.w r1, \[pc, #-124\] ; 0+66c <[^>]+>
0+6ea <[^>]+> f895 f000 pld \[r5\]
0+6ee <[^>]+> f895 f330 pld \[r5, #816\]
0+6f2 <[^>]+> f815 fc30 pld \[r5, #-48\]
@@ -596,8 +596,8 @@ Disassembly of section .text:
0+702 <[^>]+> f815 fd30 pld \[r5\], #-48
0+706 <[^>]+> f815 f000 pld \[r5, r0\]
0+70a <[^>]+> f819 f000 pld \[r9, r0\]
-0+70e <[^>]+> f89f f008 pld \[pc, #8\]
-0+712 <[^>]+> f81f fca6 pld \[pc, #-3238\]
+0+70e <[^>]+> f89f f006 pld \[pc, #6\] ; 0+716 <[^>]+>
+0+712 <[^>]+> f81f f0a8 pld \[pc, #-168\] ; 0+66c <[^>]+>
0+716 <[^>]+> e9d5 2300 ldrd r2, r3, \[r5\]
0+71a <[^>]+> e9d5 230c ldrd r2, r3, \[r5, #48\]
0+71e <[^>]+> e955 230c ldrd r2, r3, \[r5, #-48\]
===================================================================
Index: gas/testsuite/gas/arm/thumb32.s
--- gas/testsuite/gas/arm/thumb32.s (revision 84)
+++ gas/testsuite/gas/arm/thumb32.s (working copy)
@@ -194,6 +194,7 @@ branches:
bra bal.n
bra b.n
@ bl, blx have no short form.
+ .balign 4
1:
bra beq
bra bne
@@ -218,9 +219,8 @@ branches:
bra b
bra bl
bra blx
+ .balign 4
1:
-
- bx r0
bx r9
blx r0
blx r9
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