Fix tlbsx instruction for PPC440
Zack Weinberg
zack@codesourcery.com
Mon Sep 27 18:19:00 GMT 2004
Alan Modra <amodra@bigpond.net.au> writes:
> On Sat, Sep 25, 2004 at 11:52:13AM -0700, Zack Weinberg wrote:
>> It seems simplest to me to give this entire instruction family an
>> optional RT register, and not worry about which instructions are
>> supported on which subarchitectures - hence PPC403|PPC440|BOOKE.
>
> Works for me. The architecture book says that where the result is
> stored is implementation dependent.
Thanks. Here's a patch against binutils HEAD. I made the tests a bit
more comprehensive and put them with the other tlbsx tests (hence the
much longer delta to booke.d). I'm still wondering whether it's
necessary to say PPC403|PPC440|BOOKE, or whether some subset of that
would do.
zw
gas/testsuite:
* gas/ppc/booke.s: Test all variants of tlbsx instruction with
both two and three arguments.
* gas/ppc/altivec.d, gas/ppc/e500.d: Generalize file format regexp.
* gas/ppc/booke.d: Likewise. Update for new tests.
opcodes:
* ppc-opc.c (RTO): New operand-vector shorthand.
(tlbsx, tlbsx., tlbsxe, tlbsxe.): Accept either two or three
operands on all subarchitectures.
===================================================================
Index: gas/testsuite/gas/ppc/altivec.d
--- gas/testsuite/gas/ppc/altivec.d 16 Mar 2004 00:58:42 -0000 1.5
+++ gas/testsuite/gas/ppc/altivec.d 27 Sep 2004 18:14:54 -0000
@@ -2,7 +2,7 @@
#objdump: -dr
#name: AltiVec tests
-.*: +file format elf32-powerpc
+.*: +file format elf32-powerpc.*
Disassembly of section \.text:
===================================================================
Index: gas/testsuite/gas/ppc/booke.d
--- gas/testsuite/gas/ppc/booke.d 16 Mar 2004 00:58:42 -0000 1.8
+++ gas/testsuite/gas/ppc/booke.d 27 Sep 2004 18:14:54 -0000
@@ -2,7 +2,7 @@
#objdump: -dr -Mbooke
#name: BookE tests
-.*: +file format elf(32)?(64)?-powerpc
+.*: +file format elf(32)?(64)?-powerpc.*
Disassembly of section \.text:
@@ -80,65 +80,71 @@ Disassembly of section \.text:
d8: 7c 07 46 24 tlbivax r7,r8
dc: 7c 09 56 26 tlbivaxe r9,r10
e0: 7c 0b 67 24 tlbsx r11,r12
- e4: 7c 0d 77 26 tlbsxe r13,r14
- e8: 7c 00 07 a4 tlbwe
- ec: 7c 00 07 a4 tlbwe
- f0: 7c 21 0f a4 tlbwe r1,r1,1
-
-0+00000f4 <branch_target_7>:
- f4: 7c 22 1b 14 adde64 r1,r2,r3
- f8: 7c 85 37 14 adde64o r4,r5,r6
- fc: 7c e8 03 d4 addme64 r7,r8
- 100: 7d 2a 07 d4 addme64o r9,r10
- 104: 7d 6c 03 94 addze64 r11,r12
- 108: 7d ae 07 94 addze64o r13,r14
- 10c: 7e 80 04 40 mcrxr64 cr5
- 110: 7d f0 8b 10 subfe64 r15,r16,r17
- 114: 7e 53 a7 10 subfe64o r18,r19,r20
- 118: 7e b6 03 d0 subfme64 r21,r22
- 11c: 7e f8 07 d0 subfme64o r23,r24
- 120: 7f 3a 03 90 subfze64 r25,r26
- 124: 7f 7c 07 90 subfze64o r27,r28
-
-0+0000128 <branch_target_8>:
- 128: e8 22 03 28 stbe r1,50\(r2\)
- 12c: e8 64 02 89 stbue r3,40\(r4\)
- 130: 7c a6 39 fe stbuxe r5,r6,r7
- 134: 7d 09 51 be stbxe r8,r9,r10
- 138: 7d 6c 6b ff stdcxe\. r11,r12,r13
- 13c: f9 cf 00 78 stde r14,28\(r15\)
- 140: fa 11 00 59 stdue r16,20\(r17\)
- 144: 7e 53 a7 3e stdxe r18,r19,r20
- 148: 7e b6 bf 7e stduxe r21,r22,r23
- 14c: f8 38 00 3e stfde f1,12\(r24\)
- 150: f8 59 00 0f stfdue f2,0\(r25\)
- 154: 7c 7a dd be stfdxe f3,r26,r27
- 158: 7c 9c ed fe stfduxe f4,r28,r29
- 15c: 7c be ff be stfiwxe f5,r30,r31
- 160: f8 de 00 6c stfse f6,24\(r30\)
- 164: f8 fd 00 5d stfsue f7,20\(r29\)
- 168: 7d 1c dd 3e stfsxe f8,r28,r27
- 16c: 7d 3a cd 7e stfsuxe f9,r26,r25
- 170: 7f 17 b7 3c sthbrxe r24,r23,r22
- 174: ea b4 01 ea sthe r21,30\(r20\)
- 178: ea 72 02 8b sthue r19,40\(r18\)
- 17c: 7e 30 7b 7e sthuxe r17,r16,r15
- 180: 7d cd 63 3e sthxe r14,r13,r12
- 184: 7d 6a 4d 3c stwbrxe r11,r10,r9
- 188: 7d 07 31 3d stwcxe\. r8,r7,r6
- 18c: e8 a4 03 2e stwe r5,50\(r4\)
- 190: e8 62 02 8f stwue r3,40\(r2\)
- 194: 7c 22 19 7e stwuxe r1,r2,r3
- 198: 7c 85 31 3e stwxe r4,r5,r6
- 19c: 4c 00 00 66 rfci
- 1a0: 7c 60 01 06 wrtee r3
- 1a4: 7c 00 81 46 wrteei 1
- 1a8: 7c 85 02 06 mfdcrx r4,r5
- 1ac: 7c aa 3a 86 mfdcr r5,234
- 1b0: 7c e6 03 06 mtdcrx r6,r7
- 1b4: 7d 10 6b 86 mtdcr 432,r8
- 1b8: 7c 00 04 ac msync
- 1bc: 7c 09 55 ec dcba r9,r10
- 1c0: 7c 00 06 ac mbar
- 1c4: 7c 00 06 ac mbar
- 1c8: 7c 20 06 ac mbar 1
+ e4: 7d 4b 67 24 tlbsx r10,r11,r12
+ e8: 7c 0c 6f 25 tlbsx\. r12,r13
+ ec: 7d 6c 6f 25 tlbsx\. r11,r12,r13
+ f0: 7c 0d 77 26 tlbsxe r13,r14
+ f4: 7d 8d 77 26 tlbsxe r12,r13,r14
+ f8: 7c 0e 7f 27 tlbsxe\. r14,r15
+ fc: 7d ae 7f 27 tlbsxe\. r13,r14,r15
+ 100: 7c 00 07 a4 tlbwe
+ 104: 7c 00 07 a4 tlbwe
+ 108: 7c 21 0f a4 tlbwe r1,r1,1
+
+0+000010c <branch_target_7>:
+ 10c: 7c 22 1b 14 adde64 r1,r2,r3
+ 110: 7c 85 37 14 adde64o r4,r5,r6
+ 114: 7c e8 03 d4 addme64 r7,r8
+ 118: 7d 2a 07 d4 addme64o r9,r10
+ 11c: 7d 6c 03 94 addze64 r11,r12
+ 120: 7d ae 07 94 addze64o r13,r14
+ 124: 7e 80 04 40 mcrxr64 cr5
+ 128: 7d f0 8b 10 subfe64 r15,r16,r17
+ 12c: 7e 53 a7 10 subfe64o r18,r19,r20
+ 130: 7e b6 03 d0 subfme64 r21,r22
+ 134: 7e f8 07 d0 subfme64o r23,r24
+ 138: 7f 3a 03 90 subfze64 r25,r26
+ 13c: 7f 7c 07 90 subfze64o r27,r28
+
+0+0000140 <branch_target_8>:
+ 140: e8 22 03 28 stbe r1,50\(r2\)
+ 144: e8 64 02 89 stbue r3,40\(r4\)
+ 148: 7c a6 39 fe stbuxe r5,r6,r7
+ 14c: 7d 09 51 be stbxe r8,r9,r10
+ 150: 7d 6c 6b ff stdcxe\. r11,r12,r13
+ 154: f9 cf 00 78 stde r14,28\(r15\)
+ 158: fa 11 00 59 stdue r16,20\(r17\)
+ 15c: 7e 53 a7 3e stdxe r18,r19,r20
+ 160: 7e b6 bf 7e stduxe r21,r22,r23
+ 164: f8 38 00 3e stfde f1,12\(r24\)
+ 168: f8 59 00 0f stfdue f2,0\(r25\)
+ 16c: 7c 7a dd be stfdxe f3,r26,r27
+ 170: 7c 9c ed fe stfduxe f4,r28,r29
+ 174: 7c be ff be stfiwxe f5,r30,r31
+ 178: f8 de 00 6c stfse f6,24\(r30\)
+ 17c: f8 fd 00 5d stfsue f7,20\(r29\)
+ 180: 7d 1c dd 3e stfsxe f8,r28,r27
+ 184: 7d 3a cd 7e stfsuxe f9,r26,r25
+ 188: 7f 17 b7 3c sthbrxe r24,r23,r22
+ 18c: ea b4 01 ea sthe r21,30\(r20\)
+ 190: ea 72 02 8b sthue r19,40\(r18\)
+ 194: 7e 30 7b 7e sthuxe r17,r16,r15
+ 198: 7d cd 63 3e sthxe r14,r13,r12
+ 19c: 7d 6a 4d 3c stwbrxe r11,r10,r9
+ 1a0: 7d 07 31 3d stwcxe\. r8,r7,r6
+ 1a4: e8 a4 03 2e stwe r5,50\(r4\)
+ 1a8: e8 62 02 8f stwue r3,40\(r2\)
+ 1ac: 7c 22 19 7e stwuxe r1,r2,r3
+ 1b0: 7c 85 31 3e stwxe r4,r5,r6
+ 1b4: 4c 00 00 66 rfci
+ 1b8: 7c 60 01 06 wrtee r3
+ 1bc: 7c 00 81 46 wrteei 1
+ 1c0: 7c 85 02 06 mfdcrx r4,r5
+ 1c4: 7c aa 3a 86 mfdcr r5,234
+ 1c8: 7c e6 03 06 mtdcrx r6,r7
+ 1cc: 7d 10 6b 86 mtdcr 432,r8
+ 1d0: 7c 00 04 ac msync
+ 1d4: 7c 09 55 ec dcba r9,r10
+ 1d8: 7c 00 06 ac mbar
+ 1dc: 7c 00 06 ac mbar
+ 1e0: 7c 20 06 ac mbar 1
===================================================================
Index: gas/testsuite/gas/ppc/booke.s
--- gas/testsuite/gas/ppc/booke.s 10 Dec 2003 22:12:50 -0000 1.3
+++ gas/testsuite/gas/ppc/booke.s 27 Sep 2004 18:14:54 -0000
@@ -71,7 +71,13 @@ branch_target_6:
tlbivax 7, 8
tlbivaxe 9, 10
tlbsx 11, 12
+ tlbsx 10, 11, 12
+ tlbsx. 12, 13
+ tlbsx. 11, 12, 13
tlbsxe 13, 14
+ tlbsxe 12, 13, 14
+ tlbsxe. 14, 15
+ tlbsxe. 13, 14, 15
tlbwe
tlbwe 0,0,0
tlbwe 1,1,1
===================================================================
Index: gas/testsuite/gas/ppc/e500.d
--- gas/testsuite/gas/ppc/e500.d 16 Mar 2004 00:58:42 -0000 1.4
+++ gas/testsuite/gas/ppc/e500.d 27 Sep 2004 18:14:54 -0000
@@ -2,7 +2,7 @@
#objdump: -dr -Me500
#name: e500 tests
-.*: +file format elf(32)?(64)?-powerpc
+.*: +file format elf(32)?(64)?-powerpc.*
Disassembly of section \.text:
===================================================================
Index: opcodes/ppc-opc.c
--- opcodes/ppc-opc.c 9 Sep 2004 12:42:35 -0000 1.74
+++ opcodes/ppc-opc.c 27 Sep 2004 18:14:54 -0000
@@ -424,8 +424,10 @@ const struct powerpc_operand powerpc_ope
#define RTQ RSQ + 1
{ 5, 21, insert_rtq, 0, PPC_OPERAND_GPR_0 },
- /* The RS field of the tlbwe instruction, which is optional. */
+ /* The RS field of the tlbwe instruction or the RT field of the
+ tlbsx instruction, which are optional. */
#define RSO RTQ + 1
+#define RTO RSO
{ 5, 21, 0, 0, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
/* The SH field in an X or M form instruction. */
@@ -4263,12 +4265,10 @@ const struct powerpc_opcode powerpc_opco
{ "mbar", X(31,854), X_MASK, BOOKE, { MO } },
{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
-{ "tlbsx", XRC(31,914,0), X_MASK, BOOKE, { RA, RB } },
-{ "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } },
-{ "tlbsx.", XRC(31,914,1), X_MASK, BOOKE, { RA, RB } },
-{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } },
-{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } },
-{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } },
+{ "tlbsx", XRC(31,914,0), X_MASK, PPC403|PPC440|BOOKE, { RTO, RA, RB } },
+{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403|PPC440|BOOKE, { RTO, RA, RB } },
+{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RTO, RA, RB } },
+{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RTO, RA, RB } },
{ "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
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