Fix tlbsx instruction for PPC440

[Zack Weinberg]

One of our customers complained that the PPC440 tlbsx instruction
should take three register arguments.  Indeed, the PPC440 reference
manual indicates that it does.  This is another difference between IBM
and Motorola implementations of Book E - IBM's chips use the reserved
bits 6:10 as an RT register field, whereas Motorola's write the result
to MAS registers.

It seems simplest to me to give this entire instruction family an
optional RT register, and not worry about which instructions are
supported on which subarchitectures - hence PPC403|PPC440|BOOKE.
I am not sure whether all of those mask entries are necessary.

This patch is against a somewhat older version of binutils; if it's
acceptable in principle I will update it for current CVS.

zw

opcodes:
        * ppc-opc.c: Add RTO operand shorthand.
        (tlbsx, tlbsx.): Allowed for PPC440 also.  Make operands
        {RTO,RA,RB} in all cases.
        (tlbsxe, tlbsxe.): Make operands {RTO,RA,RB}.
gas/testsuite:
        * booke.s: Add tests for three-argument tlbsx and variants.
        * altivec.d, e500.d: Generalize file-format marker.
        * booke.d: Likewise.  Update for changes to booke.s.

===================================================================
Index: opcodes/ppc-opc.c
--- opcodes/ppc-opc.c	12 Jan 2004 21:44:10 -0000	1.1.3.1.2.3
+++ opcodes/ppc-opc.c	25 Sep 2004 18:47:38 -0000
@@ -417,8 +417,10 @@ const struct powerpc_operand powerpc_ope
 #define RTQ RSQ + 1
   { 5, 21, insert_rtq, 0, PPC_OPERAND_GPR },
 
-  /* The RS field of the tlbwe instruction, which is optional.  */
+  /* The RS field of the tlbwe instruction or the RT field of the
+     tlbsx instruction, which are optional (sort of).  */
 #define RSO RTQ + 1
+#define RTO RSO
   { 5, 21, 0, 0, PPC_OPERAND_GPR|PPC_OPERAND_OPTIONAL },
 
   /* The SH field in an X or M form instruction.  */
@@ -4225,12 +4227,10 @@ const struct powerpc_opcode powerpc_opco
 { "mbar",    X(31,854),	X_MASK,		BOOKE,		{ MO } },
 { "eieio",   X(31,854),	0xffffffff,	PPC,		{ 0 } },
 
-{ "tlbsx",   XRC(31,914,0), X_MASK,	BOOKE,		{ RA, RB } },
-{ "tlbsx",   XRC(31,914,0), X_MASK, 	PPC403,		{ RT, RA, RB } },
-{ "tlbsx.",  XRC(31,914,1), X_MASK,	BOOKE,		{ RA, RB } },
-{ "tlbsx.",  XRC(31,914,1), X_MASK, 	PPC403,		{ RT, RA, RB } },
-{ "tlbsxe",  XRC(31,915,0), X_MASK,	BOOKE64,	{ RA, RB } },
-{ "tlbsxe.", XRC(31,915,1), X_MASK,	BOOKE64,	{ RA, RB } },
+{ "tlbsx",   XRC(31,914,0), X_MASK, 	PPC403|PPC440|BOOKE, { RTO, RA, RB } },
+{ "tlbsx.",  XRC(31,914,1), X_MASK, 	PPC403|PPC440|BOOKE, { RTO, RA, RB } },
+{ "tlbsxe",  XRC(31,915,0), X_MASK,	BOOKE64,	{ RTO, RA, RB } },
+{ "tlbsxe.", XRC(31,915,1), X_MASK,	BOOKE64,	{ RTO, RA, RB } },
 
 { "slbmfee", X(31,915), XRA_MASK,	PPC64,		{ RT, RB } },
 
===================================================================
Index: gas/testsuite/gas/ppc/altivec.d
--- gas/testsuite/gas/ppc/altivec.d	26 Nov 2003 05:10:13 -0000	1.1.3.1.2.1
+++ gas/testsuite/gas/ppc/altivec.d	25 Sep 2004 18:47:38 -0000
@@ -2,7 +2,7 @@
 #objdump: -dr
 #name: AltiVec tests
 
-.*: +file format elf32-powerpc
+.*: +file format elf32-powerpc.*
 
 Disassembly of section \.text:
 
===================================================================
Index: gas/testsuite/gas/ppc/booke.d
--- gas/testsuite/gas/ppc/booke.d	26 Nov 2003 05:10:13 -0000	1.1.3.1.2.1
+++ gas/testsuite/gas/ppc/booke.d	25 Sep 2004 18:47:38 -0000
@@ -2,7 +2,7 @@
 #objdump: -dr -Mbooke
 #name: BookE tests
 
-.*: +file format elf(32)?(64)?-powerpc
+.*: +file format elf(32)?(64)?-powerpc.*
 
 Disassembly of section \.text:
 
@@ -136,4 +136,8 @@ Disassembly of section \.text:
  1a8:	7d 10 6b 86 	mtdcr	432,r8
  1ac:	7c 00 04 ac 	msync
  1b0:	7c 09 55 ec 	dcba	r9,r10
- 1b4:	7c 00 06 ac 	mbar	0
+ 1b4:	7c 00 06 ac 	mbar	
+ 1b8:	7d 8d 77 24 	tlbsx	r12,r13,r14
+ 1bc:	7d 8d 77 25 	tlbsx\.	r12,r13,r14
+ 1c0:	7d 8d 77 26 	tlbsxe	r12,r13,r14
+ 1c4:	7d 8d 77 27 	tlbsxe\.	r12,r13,r14
===================================================================
Index: gas/testsuite/gas/ppc/booke.s
--- gas/testsuite/gas/ppc/booke.s	2 Sep 2003 23:49:56 -0000	1.1.3.1
+++ gas/testsuite/gas/ppc/booke.s	25 Sep 2004 18:47:38 -0000
@@ -129,3 +129,9 @@ branch_target_8:
 	msync
 	dcba	9, 10
 	mbar	0
+
+# tlbsx with RT
+	tlbsx	12, 13, 14
+	tlbsx.	12, 13, 14
+	tlbsxe	12, 13, 14
+	tlbsxe.	12, 13, 14
===================================================================
Index: gas/testsuite/gas/ppc/e500.d
--- gas/testsuite/gas/ppc/e500.d	26 Nov 2003 05:10:13 -0000	1.1.3.1.2.1
+++ gas/testsuite/gas/ppc/e500.d	25 Sep 2004 18:47:38 -0000
@@ -2,7 +2,7 @@
 #objdump: -dr -Me500
 #name: e500 tests
 
-.*: +file format elf(32)?(64)?-powerpc
+.*: +file format elf(32)?(64)?-powerpc.*
 
 Disassembly of section \.text: