Adding a MIPS hardware bug work-around to GAS...

[Steven J. Hill]

Greetings.

I am trying to work-around a hardware bug for a MIPS processor that
has problems with the following sequence of instructions, regardless
of the registers being used:

    store/load/load

If instead the sequence is:

    store/nop/load/load

the hardware bug is mitigated. Currently, I have investigated changing
GCC or GAS. I think that the proper solution is to place the work-around
inside of GAS. I believe the code will need to be placed inside of
the 'append_insn' function located in 'gas/config/tc-mips.c'. From what
I can see, I can only detect the above sequence when I am getting ready
to emit the the second load instruction:

    prev_prev_insn = store
    prev_insn = load
    ip = load

It seems feasible to check for this condition and do a NOP accordingly.
Does anyone see anything wrong with this approach? I just could not
find a nice way in the MIPS .md file for GCC to do this. Thoughts?

-Steve