[mips patch RFA] redefine hilo_interlocks to include recent ISAs

cgd@broadcom.com cgd@broadcom.com
Sun Jan 25 05:21:00 GMT 2004


This patch updates hilo_interlocks to include MIPS32, MIPS64, and
later ISAs, since MIPS32/MIPS64 interlock hi/lo accesses.

The MIPS32/MIPS64 specs also document that MIPS IV interlocks the
accesses, but some MIPS IV processor manuals (see comments) document
that the separation requirement is still there.  So, "whatever."

Tested with GCC on sim (with fixed interlock warnings, so that's not
saying much 8-) as well as some real HW, mipsisa64-elf target.  Also
passes the binutils testsuite w/ no new failures.


chris
--
2004-01-24  Chris Demetriou  <cgd@broadcom.com>

	* config/tc-mips.c (hilo_interlocks): Change definition
	so that MIPS32, MIPS64 and later ISAs are included, along with
	the already-included machines.  Update comments.

Index: config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.246
diff -u -p -r1.246 tc-mips.c
--- config/tc-mips.c	14 Jan 2004 18:01:07 -0000	1.246
+++ config/tc-mips.c	25 Jan 2004 01:54:43 -0000
@@ -325,15 +325,28 @@ static int mips_32bitmode = 0;
 /* True if CPU has a ror instruction.  */
 #define CPU_HAS_ROR(CPU)	CPU_HAS_DROR (CPU)
 
-/* Whether the processor uses hardware interlocks to protect
-   reads from the HI and LO registers, and thus does not
-   require nops to be inserted.  */
+/* True if mflo and mfhi can be immediately followed by instructions
+   which write to the HI and LO registers.
 
-#define hilo_interlocks (mips_opts.arch == CPU_R4010                       \
-                         || mips_opts.arch == CPU_VR5500                   \
-                         || mips_opts.arch == CPU_RM7000                   \
-                         || mips_opts.arch == CPU_SB1                      \
-                         )
+   According to MIPS specifications, MIPS ISAs I, II, and III need
+   (at least) two instructions between the reads of HI/LO and
+   instructions which write them, and later ISAs do not.  Contradicting
+   the MIPS specifications, some MIPS IV processor user manuals (e.g.
+   the UM for the NEC Vr5000) document needing the instructions between
+   HI/LO reads and writes, as well.  Therefore, we declare only MIPS32,
+   MIPS64 and later ISAs to have the interlocks, plus any specific
+   earlier-ISA CPUs for which CPU documentation declares that the
+   instructions are really interlocked.  */
+#define hilo_interlocks \
+  (mips_opts.isa == ISA_MIPS32                        \
+   || mips_opts.isa == ISA_MIPS32R2                   \
+   || mips_opts.isa == ISA_MIPS64                     \
+   || mips_opts.isa == ISA_MIPS64R2                   \
+   || mips_opts.arch == CPU_R4010                     \
+   || mips_opts.arch == CPU_VR5500                    \
+   || mips_opts.arch == CPU_RM7000                    \
+   || mips_opts.arch == CPU_SB1                       \
+   )
 
 /* Whether the processor uses hardware interlocks to protect reads
    from the GPRs after they are loaded from memory, and thus does not






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