[patch] Fix arm VFP2 insns

Paul Brook paul@codesourcery.com
Fri Jan 9 11:13:00 GMT 2004


Patch below fixes the arm additional vfp2 opcodes (fmdrr, fmrrd, fmsrr and 
fmrrs) and adds corresponding testcase.

It also rearranges the disassembly patterns so these are used in preference to 
the generic mcrr opcode.

Ok?

Paul

2004-01-09  Paul Brook  <paul@codesourcery.com>

	* gas/config/tc-arm.c (do_vfp_reg_from_sp2): Rename from do_vfp_sp_reg2.
	(do_vfp_sp_from_reg2): New function.
	(insns): Use them.
	(do_vfp_dp_from_reg2): Check return values properly.
	* gas/testsuite/gas/arm/vfp2.s, gas/arm/vfp2.d: New test.
	* gas/testsuite/gas/arm/arm.exp: Add them.
	* opcodes/arm-opc.h (arm_opcodes): Move generic mcrr after known
	specific opcodes.

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#objdump: -dr --prefix-addresses --show-raw-insn
#name: VFP Additional instructions
#as: -mfpu=vfp

# Test the ARM VFP Double Precision instructions

.*: +file format .*arm.*

Disassembly of section .text:
0+000 <[^>]*> ec4a5b10 	fmdrr	d0, r5, sl
0+004 <[^>]*> ec5a5b10 	fmrrd	r5, sl, d0
0+008 <[^>]*> ec4a5a37 	fmsrr	r5, sl, {s15, s16}
0+00c <[^>]*> ec5a5a37 	fmrrs	r5, sl, {s15, s16}
0+010 <[^>]*> ec45ab1f 	fmdrr	d15, sl, r5
0+014 <[^>]*> ec55ab1f 	fmrrd	sl, r5, d15
0+018 <[^>]*> ec45aa38 	fmsrr	sl, r5, {s17, s18}
0+01c <[^>]*> ec55aa38 	fmrrs	sl, r5, {s17, s18}
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@ VFP2 Additional instructions
	.text
	.global F
F:
	@ First we test the basic syntax and bit patterns of the opcodes.
	@ Use a combination of r5, r10, s15, s17, d0 and d15 to exercise
	@ the full register bitpatterns

	fmdrr d0, r5, r10
	fmrrd r5, r10, d0
	fmsrr {s15, s16}, r5, r10
	fmrrs r5, r10, {s15, s16}

	fmdrr d15, r10, r5
	fmrrd r10, r5, d15
	fmsrr {s17, s18}, r10, r5
	fmrrs r10, r5, {s17, s18}



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