Macro name and comment fixes for gas/tc-mips.c

[Thiemo Seufer]

Ian Lance Taylor wrote:
> I spent some time being confused by the macro ISA_HAS_COPROC_DELAYS
> because I thought it meant something like ``this ISA requires delays
> for co-processor instructions.''  In fact, as the comment explains, it
> means something rather different, namely that the ISA requires delays
> in a variety of different situations.
> 
> I propose that we rename the macro to ISA_HAS_NONBRANCH_DELAYS to
> avoid such confusion.  This patch does that rename, and also fixes the
> comment for this macro and for the gpr_interlocks macro.
> 
> Any objections to this patch?
> 
> Ian
> 
> 
> 2004-01-07  Ian Lance Taylor  <ian@wasabisystems.com>
> 
> 	* config/tc-mips.c (ISA_HAS_NONBRANCH_DELAYS): Rename from
> 	ISA_HAS_COPROC_DELAYS.  Change all uses.
[snip]
> @@ -350,7 +350,10 @@ static int mips_32bitmode = 0;
>                           )
>  
>  /* Whether the processor uses hardware interlocks to protect reads
> -   from the GPRs, and thus does not require nops to be inserted.  */
> +   from the GPRs after they are loaded from memory, and thus does not
> +   require nops to be inserted.  This applies to instructions marked
> +   INSN_LOAD_MEMORY_DELAY.  These nops are only required at MIPS ISA
> +   level I.  */
>  #define gpr_interlocks \
>    (mips_opts.isa != ISA_MIPS1  \
>     || mips_opts.arch == CPU_VR5400  \

I wonder why the vr5[45]00 are explicitly listed here, those are
MIPS IV anyway.


Thiemo