[PATCH] SH4 Disassembly Bug

[Stubbs, Andrew]

I have discovered a problem in the SH4 disassembler.

A number of instructions are incorrectly interpreted as 'fsca'.
Additionally, a number of illegal instructions are incorrectly
interpreted as 'fsca', 'fcnvds' and 'fcnvds'.

The following (not very useful) program demonstrates the problems:

8<-------------------------->8
        .section .text
        fsca fpul,dr0
        ftrv xmtrx,fv0
        fsca fpul,dr2
        fschg
        fsca fpul,dr4
        ftrv xmtrx,fv4
        fsca fpul,dr6
        fpchg
        fsca fpul,dr8
        ftrv xmtrx,fv8
        fsca fpul,dr10
        frchg
        fsca fpul,dr12
        ftrv xmtrx,fv12
        fsca fpul,dr14
        .word 0xfffd
        nop
        fcnvds dr0,fpul
        .word 0xf1bd
        fcnvds dr2,fpul
        .word 0xf3bd
        fcnvds dr4,fpul
        .word 0xf5bd
        fcnvds dr6,fpul
        .word 0xf7bd
        fcnvds dr8,fpul
        .word 0xf9bd
        fcnvds dr10,fpul
        .word 0xfbbd
        fcnvds dr12,fpul
        .word 0xfdbd
        fcnvds dr14,fpul
        .word 0xffbd
        nop
        fcnvsd fpul,dr0
        .word 0xf1ad
        fcnvsd fpul,dr2
        .word 0xf3ad
        fcnvsd fpul,dr4
        .word 0xf5ad
        fcnvsd fpul,dr6
        .word 0xf7ad
        fcnvsd fpul,dr8
        .word 0xf9ad
        fcnvsd fpul,dr10
        .word 0xfbad
        fcnvsd fpul,dr12
        .word 0xfdad
        fcnvsd fpul,dr14
        .word 0xffad
8<-------------------------->8

This disassembles to:

a.out:     file format elf32-sh

Disassembly of section .text:

00000000 <.text>:
   0:   f0 fd           fsca    fpul,dr0
   2:   f1 fd           fsca    fpul,dr1
   4:   f2 fd           fsca    fpul,dr2
   6:   f3 fd           fsca    fpul,dr3
   8:   f4 fd           fsca    fpul,dr4
   a:   f5 fd           fsca    fpul,dr5
   c:   f6 fd           fsca    fpul,dr6
   e:   f7 fd           fpchg
  10:   f8 fd           fsca    fpul,dr8
  12:   f9 fd           fsca    fpul,dr9
  14:   fa fd           fsca    fpul,dr10
  16:   fb fd           frchg
  18:   fc fd           fsca    fpul,dr12
  1a:   fd fd           fsca    fpul,dr13
  1c:   fe fd           fsca    fpul,dr14
  1e:   ff fd           fsca    fpul,dr15
  20:   00 09           nop
  22:   f0 bd           fcnvds  dr0,fpul
  24:   f1 bd           fcnvds  dr1,fpul
  26:   f2 bd           fcnvds  dr2,fpul
  28:   f3 bd           fcnvds  dr3,fpul
  2a:   f4 bd           fcnvds  dr4,fpul
  2c:   f5 bd           fcnvds  dr5,fpul
  2e:   f6 bd           fcnvds  dr6,fpul
  30:   f7 bd           fcnvds  dr7,fpul
  32:   f8 bd           fcnvds  dr8,fpul
  34:   f9 bd           fcnvds  dr9,fpul
  36:   fa bd           fcnvds  dr10,fpul
  38:   fb bd           fcnvds  dr11,fpul
  3a:   fc bd           fcnvds  dr12,fpul
  3c:   fd bd           fcnvds  dr13,fpul
  3e:   fe bd           fcnvds  dr14,fpul
  40:   ff bd           fcnvds  dr15,fpul
  42:   00 09           nop
  44:   f0 ad           fcnvsd  fpul,dr0
  46:   f1 ad           fcnvsd  fpul,dr1
  48:   f2 ad           fcnvsd  fpul,dr2
  4a:   f3 ad           fcnvsd  fpul,dr3
  4c:   f4 ad           fcnvsd  fpul,dr4
  4e:   f5 ad           fcnvsd  fpul,dr5
  50:   f6 ad           fcnvsd  fpul,dr6
  52:   f7 ad           fcnvsd  fpul,dr7
  54:   f8 ad           fcnvsd  fpul,dr8
  56:   f9 ad           fcnvsd  fpul,dr9
  58:   fa ad           fcnvsd  fpul,dr10
  5a:   fb ad           fcnvsd  fpul,dr11
  5c:   fc ad           fcnvsd  fpul,dr12
  5e:   fd ad           fcnvsd  fpul,dr13
  60:   fe ad           fcnvsd  fpul,dr14
  62:   ff ad           fcnvsd  fpul,dr15

The fpchg and frchg only disassemble correctly because the happen to
occur further up the table than fsca.

The attached patch fixes the problem. This has been tested with 'make -k
check' in a unified tree and caused no extra failures.

-- 
Andrew Stubbs
SuperH (UK) Ltd.
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