gas and MIPS cp0 instructions

Thiemo Seufer ica2_ts@csv.ica.uni-stuttgart.de
Fri Dec 10 04:42:00 GMT 2004


Zack Weinberg wrote:
> 
> One of CodeSourcery's clients is asking me why GAS rejects
> 
>         cache 0x15,0($4)
> 
> when set to -mcpu=mips2.  They claim, quite strenuously, that 

For current GAS the -mcpu option was removed. The -march option
succeded it, while having a more consistent definition. Since
GAS has no generic cpu definition for the mips1 - mips4 ISAs,
-march=mips2 is simply an alias for -march=r6000.

> > Many of the CP0 instructions while documented in the ISA manuals,
> > are not strictly speaking part of the ISA definiton(s) themselves
> > (by MIPS Technologies).  Eret, cache, mtc0, mtc0, sync, ssnop (and
> > friends) are part of the instructions which should be treated as
> > ISA-independent.

The R6000 had no such instructions, same goes for all those R3000
successors. Treating them as ISA-independent would be wrong.

> > This is something that GNU has gotten consistantly wrong over the
> > years.  Cache is a legal instruction in MIPS-III, MIPS32, MIPS64
> > (and a few other) processors.  You can't tell if the instruction is
> > supported or not just by looking at the ISA level.
> 
> I'd like to get your collective opinion on this.

The common workaround for this problem is to use

	.set mips3
	cache 0x15,0($4)
	.set mips0

A more obvious way would be

	.set arch=r4000
	cache 0x15,0($4)
	.set arch=default

which explicitely documents the expected CPU, but this needs more
modern binutils than the -mcpu option suggests to be in use.


Thiemo



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