m68k reloc types

[Roman Zippel]

Hi,

On Tue, 17 Aug 2004, Andreas Schwab wrote:

> > Anyway, the cost of a memory indirect accesses depends on the cpu, 
> > 680[46]0 would benefit from this.
> 
> Are you sure about that?  AFAIK especially on the 040 and 060 the memory
> indirect addressing modes are slower than going through a temporary
> register.  For example on the 68040, for `add Rn,([bd,BR,Xn])' calculating
> the destination address takes a whopping 10 cycles and additionally 9
> cycles to execute the insn, whereas for simple addressing modes at most 2
> cycles are needed for both.  Thus memory indirect is a major loss.  On the
> 060 the difference is much smaller, but still significant.

It of course needs some fine tuning. But compare the timings when using 
full extension words, if you can combine two moves, which already use two 
full extension words into a single one, it's usually faster. OTOH if you 
only have 16 bit offsets or no offsets you don't want to merge them.
Combining brief extension words seem to be depend on the cpu, on the 
0[46]0 there doesn't seem to be a big difference and the resulting code 
can be smaller, otherwise it's usually slower.

bye, Roman