[PATCH-SH]:Generating proper relocations to link withRenesasSHC linker

[Kaz Kojima]

"Asgari J. Jinia" <AsgariJ@KPITCummins.com> wrote:
> Please find below complete patch which adds -renesas-relocs switch 
> to gas to generate relocations of local symbols against symbol values. 
> This enables object files generated by GNU assembler with -renesas-relocs 
> option to be correctly linked with Renesas linker.

Thanks for your patch.  I've modified your patch and ChangeLog
entries according to the GNU coding standard.  The attached one
is against current CVS.  I've reduced gas testcase and changed
the option name to simply -renesas.

Have you and Dhananjay completed the FSF copyright assignment
paperwork?  It seems this change needs the assignment with FSF.

Regards,
	kaz
--
[gas/ChangeLog]
2004-03-30  Asgari Jinia  <asgarij@kpitcummins.com>
	    Dhananjay Deshpande <dhananjayd@kpitcummins.com>

	* config/tc-sh.c (dont_adjust_reloc_32): New variable.
	(sh_fix_adjustable): Avoid adjusting BFD_RELOC_32 when
	dont_adjust_reloc_32 is set.
	(md_longopts): Add option -renesas.
        (md_parse_option, md_show_usage): Likewise.
	* doc/c-sh.texi: Likewise.

[gas/testsuite/ChangeLog]
2004-03-30  Asgari Jinia  <asgarij@kpitcummins.com>

	* gas/sh/renesas-1.s, gas/sh/renesas-1.d: New test for -renesas
	option.
	* gas/sh/basic.exp: Run the new test.

diff -u3prN ORIG/src/gas/config/tc-sh.c TMP/src/gas/config/tc-sh.c
--- ORIG/src/gas/config/tc-sh.c	Tue Mar 30 09:11:06 2004
+++ TMP/src/gas/config/tc-sh.c	Wed Mar 31 08:47:26 2004
@@ -132,6 +132,10 @@ int sh_relax;		/* set if -relax seen */
 
 int sh_small;
 
+/* Flag to generate relocations against symbol values for local symbols.  */
+
+static int dont_adjust_reloc_32;
+
 /* preset architecture set, if given; zero otherwise.  */
 
 static int preset_target_arch;
@@ -2883,6 +2887,7 @@ struct option md_longopts[] =
 #define OPTION_SMALL (OPTION_LITTLE + 1)
 #define OPTION_DSP (OPTION_SMALL + 1)
 #define OPTION_ISA                    (OPTION_DSP + 1)
+#define OPTION_RENESAS (OPTION_ISA + 1)
 
   {"relax", no_argument, NULL, OPTION_RELAX},
   {"big", no_argument, NULL, OPTION_BIG},
@@ -2890,8 +2895,10 @@ struct option md_longopts[] =
   {"small", no_argument, NULL, OPTION_SMALL},
   {"dsp", no_argument, NULL, OPTION_DSP},
   {"isa",                    required_argument, NULL, OPTION_ISA},
+  {"renesas", no_argument, NULL, OPTION_RENESAS},
+
 #ifdef HAVE_SH64
-#define OPTION_ABI                    (OPTION_ISA + 1)
+#define OPTION_ABI                    (OPTION_RENESAS + 1)
 #define OPTION_NO_MIX                 (OPTION_ABI + 1)
 #define OPTION_SHCOMPACT_CONST_CRANGE (OPTION_NO_MIX + 1)
 #define OPTION_NO_EXPAND              (OPTION_SHCOMPACT_CONST_CRANGE + 1)
@@ -2932,6 +2939,10 @@ md_parse_option (int c, char *arg ATTRIB
       preset_target_arch = arch_sh1_up & ~arch_sh2e_up;
       break;
 
+    case OPTION_RENESAS:
+      dont_adjust_reloc_32 = 1;
+      break;
+
     case OPTION_ISA:
       if (strcasecmp (arg, "sh4") == 0)
 	preset_target_arch = arch_sh4;
@@ -3019,6 +3030,8 @@ SH options:\n\
 -little			generate little endian code\n\
 -big			generate big endian code\n\
 -relax			alter jump instructions for long displacements\n\
+-renesas		disable optimization with section symbol for\n\
+			compatibility with Renesas assembler.\n\
 -small			align sections to 4 byte boundaries, not 16\n\
 -dsp			enable sh-dsp insns, and disable floating-point ISAs.\n\
 -isa=[sh4\n\
@@ -3564,6 +3577,7 @@ sh_fix_adjustable (fixS *fixP)
   if (fixP->fx_r_type == BFD_RELOC_32_PLT_PCREL
       || fixP->fx_r_type == BFD_RELOC_32_GOT_PCREL
       || fixP->fx_r_type == BFD_RELOC_SH_GOTPC
+      || ((fixP->fx_r_type == BFD_RELOC_32) && dont_adjust_reloc_32)
       || fixP->fx_r_type == BFD_RELOC_RVA)
     return 0;
 
diff -u3prN ORIG/src/gas/doc/c-sh.texi TMP/src/gas/doc/c-sh.texi
--- ORIG/src/gas/doc/c-sh.texi	Sat Jan 10 23:17:10 2004
+++ TMP/src/gas/doc/c-sh.texi	Wed Mar 31 08:47:26 2004
@@ -29,6 +29,7 @@
 @kindex -relax
 @kindex -small
 @kindex -dsp
+@kindex -renesas
 
 @item -little
 Generate little endian code.
@@ -44,6 +45,10 @@ Align sections to 4 byte boundaries, not
 
 @item -dsp
 Enable sh-dsp insns, and disable sh3e / sh4 insns.
+
+@item -renesas
+Disable optimization with section symbol for compatibility with
+Renesas assembler.
 
 @item -isa=sh4 | sh4a
 Specify the sh4 or sh4a instruction set.
diff -u3prN ORIG/src/gas/testsuite/gas/sh/basic.exp TMP/src/gas/testsuite/gas/sh/basic.exp
--- ORIG/src/gas/testsuite/gas/sh/basic.exp	Mon Feb  9 21:38:31 2004
+++ TMP/src/gas/testsuite/gas/sh/basic.exp	Wed Mar 31 10:17:27 2004
@@ -157,6 +157,9 @@ if [istarget sh*-*-*] then {
 	run_dump_test "tlspic"
 
 	run_dump_test "tlsnopic"
+
+	# Test -renesas.
+	run_dump_test "renesas-1"
     }
 }
 
diff -u3prN ORIG/src/gas/testsuite/gas/sh/renesas-1.d TMP/src/gas/testsuite/gas/sh/renesas-1.d
--- ORIG/src/gas/testsuite/gas/sh/renesas-1.d	Thu Jan  1 09:00:00 1970
+++ TMP/src/gas/testsuite/gas/sh/renesas-1.d	Wed Mar 31 08:47:26 2004
@@ -0,0 +1,11 @@
+#objdump: -dr
+#as: -renesas
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <foo-0x4>:
+   0:	00 00 [ 	]*\.word 0x0000
+[ 	]+0: R_SH_DIR32	foo
+	\.\.\.
diff -u3prN ORIG/src/gas/testsuite/gas/sh/renesas-1.s TMP/src/gas/testsuite/gas/sh/renesas-1.s
--- ORIG/src/gas/testsuite/gas/sh/renesas-1.s	Thu Jan  1 09:00:00 1970
+++ TMP/src/gas/testsuite/gas/sh/renesas-1.s	Wed Mar 31 08:47:26 2004
@@ -0,0 +1,3 @@
+	.text
+	.long	foo
+foo: