[PATCH] Add .set arch=FOO support to MIPS gas.

cgd@broadcom.com cgd@broadcom.com
Sun Jun 29 04:52:00 GMT 2003


At Sat, 28 Jun 2003 22:48:25 +0000 (UTC), "Thiemo Seufer" wrote:
> this extends the .set directive to allow
> 
> 	.set arch=FOO
> 
> 	# some code for CPU FOO
> 
> 	.set arch=default
> 
> This allows code for different MIPS CPUs in one file.
> It can be seen as a more specific version of ".set mipsX".

I'm glad to see this; i've had this on my big list of "relatively easy"
things to implement for a while, but hadn't gotten close to it.


> @@ -12464,6 +12473,47 @@ s_mipsset (x)
>  	  free (s);
>  	}
>      }
> +  else if (strncmp (name, "arch=", 5) == 0)
> +    {
> +      /* Permit the user to change the architecture on the fly.  Needless
> +	 to say, misuse can cause serious problems.  */
> +      if (strcmp (name + 5, "default") == 0)
> +	{
> +	  mips_opts.arch = file_mips_arch;
> +	  mips_opts.isa = file_mips_isa;
> +	  mips_opts.gp32 = file_mips_gp32;
> +	  mips_opts.fp32 = file_mips_fp32;
> +	}
> +      else
> +	{
> +	  const struct mips_cpu_info *p;
> +
> +	  p = mips_parse_cpu("internal use", name + 5);
> +	  if (!p)
> +	    as_bad (_("unknown architecture %s"), name + 5);
> +	  else
> +	    {
> +	      mips_opts.arch = p->cpu;
> +	      mips_opts.isa = p->isa;
> +	    }
> +
> +	  switch (mips_opts.arch)
> +	    {
> +	      case CPU_R3000:
> +	      case CPU_R3900:
> +	      case CPU_R6000:
> +	      case CPU_MIPS32:
> +	      case CPU_MIPS32R2:
> +		mips_opts.gp32 = 1;
> +		mips_opts.fp32 = 1;
> +		break;
> +	      default:
> +		mips_opts.gp32 = 0;
> +		mips_opts.fp32 = 0;
> +		break;
> +	    }
> +	}
> +    }
>    else
>      {
>        as_warn (_("Tried to set unrecognized symbol: %s\n"), name);

personally, i think i'd actually stuff the 'mipsN' and 'arch=' into
the same outer 'if' check  (i.e., look for arch= and mips*, then do
the right thing for each inside).

If you don't do that and don't otherwise share the switch stmt (hey,
I'm OK w/ goto... 8-), i'd advise copying the other one verbatim and
making comments in both places.

(Well, I suppose there might be a reason to do the above based on arch
rather than ISA, but I can't figure it.  Do you have some reason to
not do it exactly the same?)

combining them into the same option makes the code a bit deeper, but
the 'weird' part is the switch statement above, so best to keep that
in one place IMO.  Plus, leads to less maintenance long term if there
are more 32-bit core variants.


Hmm, completely unrelated, but looking to see if you got all of the
32-bit arches:

  { "r4010",          0,      ISA_MIPS2,      CPU_R4010 },

in the MIPS III section of the table.  This appears to be an LSI
R4010, rather than the R4010 which seems to be the name for the
R4000/R4400 FP coprocessor.  8-S

anybody know what the right thing is there?  The disassembler says
that it's:

  { "r4010",    1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
    mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },

So, I think you missed this one (and it illustrates why IMO it's
better to do the switch by ISA 8-).


(really glad to see this patch.  thanks.)


cgd



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