Add SH2E support

Nick Clifton nickc@redhat.com
Thu Jan 23 18:51:00 GMT 2003


Hi Guys,

  I am contributing the SH2E support developed by Alexandre Oliva and
  Elena Zannoni at Red Hat.

Cheers
        Nick


include/ChangeLog
2003-01-23  Nick Clifton  <nickc@redhat.com>

	* Add sh2e support:

	2002-04-02  Alexandre Oliva  <aoliva@redhat.com>

	 	* sh.h (EF_SH_MERGE_MACH): Handle SH2E.

	2002-04-02  Elena Zannoni  <ezannoni@redhat.com>

		* sh.h (EF_SH2E): New.

bfd/ChangeLog
2003-01-23  Nick Clifton  <nickc@redhat.com>

	* Add sh2e support:

	2002-04-02  Elena Zannoni  <ezannoni@redhat.com>

		* archures.c (bfd_mach_sh2e): Added.
		* bfd-in2.h: Rebuilt.
		* cpu-sh.c (arch_info_struct): Added SH2e.
		* elf32-sh.c (sh_elf_set_mach_from_flags): Handle EF_SH2E.

opcodes/ChangeLog
2003-01-23  Nick Clifton  <nickc@redhat.com>

	* Add sh2e support:

	2002-04-02  Alexandre Oliva  <aoliva@redhat.com>

		* sh-dis.c (print_insn_shx): Handle bfd_mach_sh2e.
		* sh-opc.h (arch_sh2e, arch_sh2e_up): New.
		(arch_sh2_up): Added sh2e.
		(sh_table): Replaced all occurrences of arch_sh3e_up with
		arch_sh2e_up, except in fsqrt.

gas/ChangeLog
2003-01-23  Nick Clifton  <nickc@redhat.com>

        NEWS: Announce sh2e support.

        * Add sh2e support:

	2002-04-02  Alexandre Oliva  <aoliva@redhat.com>

		* config/tc-sh.c (md_show_usage): Added sh2e next to
		sh3e.
		(sh_elf_final_processing): Handle arch_sh2e.


Index: include/elf/sh.h
===================================================================
RCS file: /cvs/src/src/include/elf/sh.h,v
retrieving revision 1.12
diff -c -3 -p -w -r1.12 sh.h
*** include/elf/sh.h	23 Jan 2003 11:51:31 -0000	1.12
--- include/elf/sh.h	23 Jan 2003 17:19:25 -0000
***************
*** 33,38 ****
--- 33,39 ----
  #define EF_SH_HAS_FP(flags) ((flags) & 8)
  #define EF_SH3E		   8
  #define EF_SH4		   9
+ #define EF_SH2E            11
  
  /* This one can only mix in objects from other EF_SH5 objects.  */
  #define EF_SH5		  10
***************
*** 45,50 ****
--- 46,58 ----
     : (((mach1) < EF_SH3 && (mach2) == EF_SH_UNKNOWN) \
        || ((mach2) < EF_SH3 && (mach1) == EF_SH_UNKNOWN)) \
     ? EF_SH3 \
+    : ((mach1) == EF_SH2E && EF_SH_HAS_FP (mach2)) \
+    ? (mach2) \
+    : ((mach2) == EF_SH2E && EF_SH_HAS_FP (mach1)) \
+    ? (mach1) \
+    : (((mach1) == EF_SH2E && (mach2) == EF_SH_UNKNOWN) \
+       || ((mach2) == EF_SH2E && (mach1) == EF_SH_UNKNOWN)) \
+    ? EF_SH2E \
     : (((mach1) == EF_SH3E && (mach2) == EF_SH_UNKNOWN) \
        || ((mach2) == EF_SH3E && (mach1) == EF_SH_UNKNOWN)) \
     ? EF_SH4 \

Index: bfd/archures.c
===================================================================
RCS file: /cvs/src/src/bfd/archures.c,v
retrieving revision 1.64
diff -c -3 -p -w -r1.64 archures.c
*** bfd/archures.c	3 Jan 2003 21:12:23 -0000	1.64
--- bfd/archures.c	23 Jan 2003 17:19:29 -0000
*************** DESCRIPTION
*** 213,218 ****
--- 213,219 ----
  .#define bfd_mach_sh            1
  .#define bfd_mach_sh2        0x20
  .#define bfd_mach_sh_dsp     0x2d
+ .#define bfd_mach_sh2e       0x2e
  .#define bfd_mach_sh3        0x30
  .#define bfd_mach_sh3_dsp    0x3d
  .#define bfd_mach_sh3e       0x3e

Index: bfd/cpu-sh.c
===================================================================
RCS file: /cvs/src/src/bfd/cpu-sh.c,v
retrieving revision 1.9
diff -c -3 -p -w -r1.9 cpu-sh.c
*** bfd/cpu-sh.c	30 Nov 2002 08:39:36 -0000	1.9
--- bfd/cpu-sh.c	23 Jan 2003 17:19:31 -0000
*************** compatible (a,b)
*** 40,52 ****
  
  #define SH_NEXT      &arch_info_struct[0]
  #define SH2_NEXT     &arch_info_struct[1]
! #define SH_DSP_NEXT  &arch_info_struct[2]
! #define SH3_NEXT     &arch_info_struct[3]
! #define SH3_DSP_NEXT &arch_info_struct[4]
! #define SH3E_NEXT    &arch_info_struct[5]
! #define SH4_NEXT     NULL
! #undef  SH4_NEXT
! #define SH4_NEXT     &arch_info_struct[6]
  #define SH64_NEXT    NULL
  
  static const bfd_arch_info_type arch_info_struct[] =
--- 40,51 ----
  
  #define SH_NEXT      &arch_info_struct[0]
  #define SH2_NEXT     &arch_info_struct[1]
! #define SH2E_NEXT    &arch_info_struct[2]
! #define SH_DSP_NEXT  &arch_info_struct[3]
! #define SH3_NEXT     &arch_info_struct[4]
! #define SH3_DSP_NEXT &arch_info_struct[5]
! #define SH3E_NEXT    &arch_info_struct[6]
! #define SH4_NEXT     &arch_info_struct[7]
  #define SH64_NEXT    NULL
  
  static const bfd_arch_info_type arch_info_struct[] =
*************** static const bfd_arch_info_type arch_inf
*** 64,69 ****
--- 63,82 ----
      bfd_default_compatible,
      bfd_default_scan,
      SH2_NEXT
+   },
+   {
+     32,				/* 32 bits in a word */
+     32,				/* 32 bits in an address */
+     8,				/* 8 bits in a byte */
+     bfd_arch_sh,
+     bfd_mach_sh2e,
+     "sh",			/* arch_name  */
+     "sh2e",			/* printable name */
+     1,
+     FALSE,			/* not the default */
+     bfd_default_compatible,
+     bfd_default_scan,
+     SH2E_NEXT
    },
    {
      32,				/* 32 bits in a word */

Index: bfd/elf32-sh.c
===================================================================
RCS file: /cvs/src/src/bfd/elf32-sh.c,v
retrieving revision 1.69
diff -c -3 -p -w -r1.69 elf32-sh.c
*** bfd/elf32-sh.c	20 Jan 2003 18:06:21 -0000	1.69
--- bfd/elf32-sh.c	23 Jan 2003 17:19:37 -0000
*************** sh_elf_set_mach_from_flags (abfd)
*** 6724,6729 ****
--- 6724,6732 ----
      case EF_SH2:
        bfd_default_set_arch_mach (abfd, bfd_arch_sh, bfd_mach_sh2);
        break;
+     case EF_SH2E:
+       bfd_default_set_arch_mach (abfd, bfd_arch_sh, bfd_mach_sh2e);
+       break;
      case EF_SH_DSP:
        bfd_default_set_arch_mach (abfd, bfd_arch_sh, bfd_mach_sh_dsp);
        break;

Index: opcodes/sh-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/sh-dis.c,v
retrieving revision 1.15
diff -c -3 -p -w -r1.15 sh-dis.c
*** opcodes/sh-dis.c	2 Dec 2002 13:13:37 -0000	1.15
--- opcodes/sh-dis.c	23 Jan 2003 17:19:43 -0000
*************** print_insn_sh (memaddr, info)
*** 314,319 ****
--- 314,322 ----
        break;
      case bfd_mach_sh2:
        target_arch = arch_sh2;
+       break;
+     case bfd_mach_sh2e:
+       target_arch = arch_sh2e;
        break;
      case bfd_mach_sh_dsp:
        target_arch = arch_sh_dsp;

Index: opcodes/sh-opc.h
===================================================================
RCS file: /cvs/src/src/opcodes/sh-opc.h,v
retrieving revision 1.14
diff -c -3 -p -w -r1.14 sh-opc.h
*** opcodes/sh-opc.h	18 Nov 2002 16:50:04 -0000	1.14
--- opcodes/sh-opc.h	23 Jan 2003 17:19:44 -0000
*************** typedef enum {
*** 135,159 ****
  	FPUL_M,
  	FPSCR_N,
  	FPSCR_M
! } sh_arg_type;
  
! typedef enum {
    A_A1_NUM =   5,
    A_A0_NUM =   7,
    A_X0_NUM, A_X1_NUM, A_Y0_NUM, A_Y1_NUM,
    A_M0_NUM, A_A1G_NUM, A_M1_NUM, A_A0G_NUM
! } sh_dsp_reg_nums;
  
  #define arch_sh1     0x0001
  #define arch_sh2     0x0002
  #define arch_sh3     0x0004
  #define arch_sh3e    0x0008
  #define arch_sh4     0x0010
  #define arch_sh_dsp  0x0100
  #define arch_sh3_dsp 0x0200
  
  #define arch_sh1_up (arch_sh1 | arch_sh2_up)
! #define arch_sh2_up (arch_sh2 | arch_sh3_up | arch_sh_dsp)
  #define arch_sh3_up (arch_sh3 | arch_sh3e_up | arch_sh3_dsp)
  #define arch_sh3e_up (arch_sh3e | arch_sh4_up)
  #define arch_sh4_up arch_sh4
--- 138,167 ----
      FPUL_M,
      FPSCR_N,
      FPSCR_M
!   }
! sh_arg_type;
  
! typedef enum
!   {
      A_A1_NUM =   5,
      A_A0_NUM =   7,
      A_X0_NUM, A_X1_NUM, A_Y0_NUM, A_Y1_NUM,
      A_M0_NUM, A_A1G_NUM, A_M1_NUM, A_A0G_NUM
!   }
! sh_dsp_reg_nums;
  
  #define arch_sh1     0x0001
  #define arch_sh2     0x0002
  #define arch_sh3     0x0004
  #define arch_sh3e    0x0008
  #define arch_sh4     0x0010
+ #define arch_sh2e    0x0020
  #define arch_sh_dsp  0x0100
  #define arch_sh3_dsp 0x0200
  
  #define arch_sh1_up  (arch_sh1 | arch_sh2_up)
! #define arch_sh2_up  (arch_sh2 | arch_sh2e_up | arch_sh3_up | arch_sh_dsp)
! #define arch_sh2e_up (arch_sh2e | arch_sh3e_up)
  #define arch_sh3_up  (arch_sh3 | arch_sh3e_up | arch_sh3_dsp)
  #define arch_sh3e_up (arch_sh3e | arch_sh4_up)
  #define arch_sh4_up  arch_sh4
*************** const sh_opcode_info sh_table[] = {
*** 306,314 ****
  
  /* 0100nnnn10111010 lds <REG_N>,Y1	*/{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up},
  
! /* 0100nnnn01011010 lds <REG_N>,FPUL    */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh3e_up},
  
! /* 0100nnnn01101010 lds <REG_M>,FPSCR   */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh3e_up},
  
  /* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh1_up},
  
--- 315,323 ----
  
  /* 0100nnnn10111010 lds <REG_N>,Y1	*/{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up},
  
! /* 0100nnnn01011010 lds <REG_N>,FPUL    */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up},
    
! /* 0100nnnn01101010 lds <REG_M>,FPSCR   */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up},
  
  /* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh1_up},
  
*************** const sh_opcode_info sh_table[] = {
*** 328,336 ****
  
  /* 0100nnnn10110110 lds.l @<REG_N>+,Y1	*/{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up},
  
! /* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh3e_up},
  
! /* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh3e_up},
  
  /* 0000000000111000 ldtlb               */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up},
  
--- 337,345 ----
  
  /* 0100nnnn10110110 lds.l @<REG_N>+,Y1	*/{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up},
  
! /* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up},
    
! /* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up},
  
  /* 0000000000111000 ldtlb               */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up},
  
*************** const sh_opcode_info sh_table[] = {
*** 551,559 ****
  
  /* 0000nnnn10111010 sts Y1,<REG_N>	*/{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up},
  
! /* 0000nnnn01011010 sts FPUL,<REG_N>    */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh3e_up},
  
! /* 0000nnnn01101010 sts FPSCR,<REG_N>   */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh3e_up},
  
  /* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh1_up},
  
--- 560,568 ----
  
  /* 0000nnnn10111010 sts Y1,<REG_N>	*/{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up},
  
! /* 0000nnnn01011010 sts FPUL,<REG_N>    */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up},
    
! /* 0000nnnn01101010 sts FPSCR,<REG_N>   */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up},
  
  /* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh1_up},
  
*************** const sh_opcode_info sh_table[] = {
*** 573,581 ****
  
  /* 0100nnnn10110110 sts.l Y1,@-<REG_N>	*/{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up},
  
! /* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh3e_up},
  
! /* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh3e_up},
  
  /* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh1_up},
  
--- 582,590 ----
  
  /* 0100nnnn10110110 sts.l Y1,@-<REG_N>	*/{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up},
  
! /* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up},
    
! /* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up},
  
  /* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh1_up},
  
*************** const sh_opcode_info sh_table[] = {
*** 736,792 ****
  /* 11111101xxyynnnn plds <DSP_REG_N>,MACL */
  {"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up},
  
! /* 1111nnnn01011101 fabs <F_REG_N>     */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh3e_up},
  /* 1111nnnn01011101 fabs <D_REG_N>     */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh4_up},
  
! /* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh3e_up},
  /* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh4_up},
  
! /* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh3e_up},
  /* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh4_up},
  
! /* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh3e_up},
  /* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh4_up},
  
  /* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_B,HEX_D}, arch_sh4_up},
  
  /* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_A,HEX_D}, arch_sh4_up},
  
! /* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh3e_up},
  /* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh4_up},
  
  /* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up},
  
! /* 1111nnnn10001101 fldi0 <F_REG_N>    */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh3e_up},
  
! /* 1111nnnn10011101 fldi1 <F_REG_N>    */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh3e_up},
  
! /* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh3e_up},
  
! /* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh3e_up},
  /* 1111nnnn00101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh4_up},
  
! /* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh3e_up},
  
! /* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh3e_up},
  /* 1111nnnnmmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh4_up},
  
! /* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh3e_up},
  /* 1111nnnnmmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up},
  
! /* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh3e_up},
  /* 1111nnnnmmmm1010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up},
  
! /* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh3e_up},
  /* 1111nnnnmmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up},
  
! /* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh3e_up},
  /* 1111nnnnmmmm1011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up},
  
! /* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh3e_up},
  /* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up},
  
! /* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh3e_up},
  /* 1111nnnnmmmm0111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up},
  
  /* 1111nnnnmmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up},
--- 745,801 ----
  /* 11111101xxyynnnn plds <DSP_REG_N>,MACL */
  {"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up},
  
! /* 1111nnnn01011101 fabs <F_REG_N>     */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up},
  /* 1111nnnn01011101 fabs <D_REG_N>     */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh4_up},
  
! /* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up},
  /* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh4_up},
  
! /* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up},
  /* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh4_up},
  
! /* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up},
  /* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh4_up},
  
  /* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_B,HEX_D}, arch_sh4_up},
  
  /* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_A,HEX_D}, arch_sh4_up},
  
! /* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up},
  /* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh4_up},
  
  /* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up},
  
! /* 1111nnnn10001101 fldi0 <F_REG_N>    */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up},
  
! /* 1111nnnn10011101 fldi1 <F_REG_N>    */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up},
  
! /* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up},
  
! /* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up},
  /* 1111nnnn00101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh4_up},
  
! /* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up},
  
! /* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up},
  /* 1111nnnnmmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh4_up},
  
! /* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up},
  /* 1111nnnnmmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up},
  
! /* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up},
  /* 1111nnnnmmmm1010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up},
  
! /* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up},
  /* 1111nnnnmmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up},
  
! /* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up},
  /* 1111nnnnmmmm1011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up},
  
! /* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up},
  /* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up},
  
! /* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up},
  /* 1111nnnnmmmm0111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up},
  
  /* 1111nnnnmmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up},
*************** const sh_opcode_info sh_table[] = {
*** 801,822 ****
  
  /* 1111nnnnmmmm0111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up},
  
! /* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh3e_up},
  
! /* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh3e_up},
  
! /* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh3e_up},
  
! /* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh3e_up},
  
! /* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh3e_up},
  
! /* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh3e_up},
  
! /* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh3e_up},
  /* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh4_up},
  
! /* 1111nnnn01001101 fneg <F_REG_N>     */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh3e_up},
  /* 1111nnnn01001101 fneg <D_REG_N>     */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh4_up},
  
  /* 1111101111111101 frchg               */{"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}, arch_sh4_up},
--- 810,831 ----
  
  /* 1111nnnnmmmm0111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up},
  
! /* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up},
  
! /* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up},
  
! /* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up},
  
! /* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up},
  
! /* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up},
  
! /* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up},
  
! /* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up},
  /* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh4_up},
  
! /* 1111nnnn01001101 fneg <F_REG_N>     */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up},
  /* 1111nnnn01001101 fneg <D_REG_N>     */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh4_up},
  
  /* 1111101111111101 frchg               */{"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}, arch_sh4_up},
*************** const sh_opcode_info sh_table[] = {
*** 826,837 ****
  /* 1111nnnn01101101 fsqrt <F_REG_N>    */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh3e_up},
  /* 1111nnnn01101101 fsqrt <D_REG_N>    */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh4_up},
  
! /* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh3e_up},
  
! /* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh3e_up},
  /* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh4_up},
  
! /* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh3e_up},
  /* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh4_up},
  
  /* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_NM,HEX_F,HEX_D}, arch_sh4_up},
--- 835,846 ----
  /* 1111nnnn01101101 fsqrt <F_REG_N>    */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh3e_up},
  /* 1111nnnn01101101 fsqrt <D_REG_N>    */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh4_up},
  
! /* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up},
  
! /* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up},
  /* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh4_up},
  
! /* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up},
  /* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh4_up},
  
  /* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_NM,HEX_F,HEX_D}, arch_sh4_up},

Index: gas/config/tc-sh.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-sh.c,v
retrieving revision 1.79
diff -c -3 -p -w -r1.79 tc-sh.c
*** gas/config/tc-sh.c	23 Jan 2003 12:51:05 -0000	1.79
--- gas/config/tc-sh.c	23 Jan 2003 17:19:54 -0000
*************** SH options:\n\
*** 2718,2724 ****
  -big			generate big endian code\n\
  -relax			alter jump instructions for long displacements\n\
  -small			align sections to 4 byte boundaries, not 16\n\
! -dsp			enable sh-dsp insns, and disable sh3e / sh4 insns.\n"));
  #ifdef HAVE_SH64
    fprintf (stream, _("\
  -isa=[shmedia		set default instruction set for SH64\n\
--- 2718,2724 ----
  -big			generate big endian code\n\
  -relax			alter jump instructions for long displacements\n\
  -small			align sections to 4 byte boundaries, not 16\n\
! -dsp			enable sh-dsp insns, and disable sh2e/sh3e/sh4 insns.\n"));
  #ifdef HAVE_SH64
    fprintf (stream, _("\
  -isa=[shmedia		set default instruction set for SH64\n\
*************** sh_elf_final_processing ()
*** 3298,3303 ****
--- 3298,3305 ----
      val = EF_SH1;
    else if (valid_arch & arch_sh2)
      val = EF_SH2;
+   else if (valid_arch & arch_sh2e)
+     val = EF_SH2E;
    else if (valid_arch & arch_sh_dsp)
      val = EF_SH_DSP;
    else if (valid_arch & arch_sh3)

Index: gas/NEWS
===================================================================
RCS file: /cvs/src/src/gas/NEWS,v
retrieving revision 1.37
diff -c -3 -p -w -r1.37 NEWS
*** gas/NEWS	2 Dec 2002 15:42:08 -0000	1.37
--- gas/NEWS	23 Jan 2003 18:37:57 -0000
***************
*** 1,5 ****
--- 1,7 ----
  -*- text -*-
  
+ * Support for SH2E added.
+ 
  * GASP has now been removed.
  
  * Support for Texas Instruments TMS320C4x and TMS320C3x series of



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