PATCH: ARM V6 instructions in GAS
Mark Mitchell
mark@codesourcery.com
Mon Dec 15 05:06:00 GMT 2003
On Thu, 2003-12-11 at 23:50, Alan Modra wrote:
> On Fri, Dec 05, 2003 at 05:26:25PM -0800, Mark Mitchell wrote:
> > On Fri, 2003-12-05 at 04:07, Richard Earnshaw wrote:
> > > > mark@codesourcery.com said:
> > > > > This patch adds support for the ARM V6 architecture to GAS, including
> > > > > both the new ARM and new THUMB instructions.
>
> --target=arm-aout gas testsuite
> +FAIL: THUMB V6 instructions
The attached patch (diffs) (checked in) fixes this failure. This issue
was due to an oddity in the aout file format, and I fixed it by using
the same approach used for other ARM tests.
> --target=arm-coff gas testsuite
> +FAIL: ARM V6 instructions
The core problem is that in COFF mode we do not really know what machine
architecture is being used in the assembly file.
See this comment in coffcode.h:
/* The COFF header does not have enough bits available
to cover all the different ARM architectures. So
we interpret F_ARM_5, the highest flag value to mean
"the highest ARM architecture known to BFD" which is
currently the XScale. */
We mistakenly think that the code was generated for XScale and try to
disassemble it accordingly, which gets us the wrong answer for two
instructions in the .s file.
I tried updating things so that F_ARM_5 implied ARM V6, but that isn't
really right because there is no proper notion of "the highest ARM
architecture known to BFD" once we have both XScale and ARM V6. Neither
is a superset of the other.
So, I checked in the attached patch (diffs2) which gives priority to V6
instructions over XScale instructions when disassembling. That approach
should be correct, in that the V6 instructions were designed not to
conflict with the XScale instructions.
--
Mark Mitchell <mark@codesourcery.com>
CodeSourcery, LLC
-------------- next part --------------
2003-12-14 Mark Mitchell <mark@codesourcery.com>
* gas/arm/thumbv6.s: Add nops.
* gas/arm/thumbv6.d: Use -M force-thumb option to objdump. Add nops.
Index: gas/arm/thumbv6.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/thumbv6.d,v
retrieving revision 1.1
diff -c -5 -p -r1.1 thumbv6.d
*** gas/arm/thumbv6.d 6 Dec 2003 01:25:29 -0000 1.1
--- gas/arm/thumbv6.d 15 Dec 2003 04:43:47 -0000
***************
*** 1,8 ****
#name: THUMB V6 instructions
#as: -march=armv6 -mthumb
! #objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format .*arm.*
Disassembly of section .text:
0+000 <[^>]*> b666 * cpsie ai
--- 1,8 ----
#name: THUMB V6 instructions
#as: -march=armv6 -mthumb
! #objdump: -dr --prefix-addresses --show-raw-insn -M force-thumb
.*: +file format .*arm.*
Disassembly of section .text:
0+000 <[^>]*> b666 * cpsie ai
*************** Disassembly of section .text:
*** 15,19 ****
--- 15,23 ----
0+00e <[^>]*> b650 * setend le
0+010 <[^>]*> b208 * sxth r0, r1
0+012 <[^>]*> b251 * sxtb r1, r2
0+014 <[^>]*> b2a3 * uxth r3, r4
0+016 <[^>]*> b2f5 * uxtb r5, r6
+ 0+018 <[^>]*> 46c0 * nop[ ]+\(mov r8, r8\)
+ 0+01a <[^>]*> 46c0 * nop[ ]+\(mov r8, r8\)
+ 0+01c <[^>]*> 46c0 * nop[ ]+\(mov r8, r8\)
+ 0+01e <[^>]*> 46c0 * nop[ ]+\(mov r8, r8\)
Index: gas/arm/thumbv6.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/thumbv6.s,v
retrieving revision 1.1
diff -c -5 -p -r1.1 thumbv6.s
*** gas/arm/thumbv6.s 6 Dec 2003 01:25:29 -0000 1.1
--- gas/arm/thumbv6.s 15 Dec 2003 04:43:47 -0000
*************** label:
*** 13,17 ****
--- 13,24 ----
setend le
sxth r0, r1
sxtb r1, r2
uxth r3, r4
uxtb r5, r6
+
+ # Add four nop instructions to ensure that the output is
+ # 32-byte aligned as required for arm-aout.
+ nop
+ nop
+ nop
+ nop
-------------- next part --------------
2003-12-14 Mark Mitchell <mark@codesourcery.com>
* arm-opc.h (arm_opcodes): Put V6 instructions before XScale
instructions.
Index: arm-opc.h
===================================================================
RCS file: /cvs/src/src/opcodes/arm-opc.h,v
retrieving revision 1.15
diff -c -5 -p -r1.15 arm-opc.h
*** arm-opc.h 6 Dec 2003 01:25:29 -0000 1.15
--- arm-opc.h 15 Dec 2003 05:00:14 -0000
*************** static const struct arm_opcode arm_opcod
*** 96,169 ****
{0x00200090, 0x0fe000f0, "mla%c%20's\t%16-19r, %0-3r, %8-11r, %12-15r"},
{0x01000090, 0x0fb00ff0, "swp%c%22'b\t%12-15r, %0-3r, [%16-19r]"},
{0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
{0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
- /* V5J instruction. */
- {0x012fff20, 0x0ffffff0, "bxj%c\t%0-3r"},
-
- /* XScale instructions. */
- {0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"},
- {0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"},
- {0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
- {0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
- {0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
- {0xf450f000, 0xfc70f000, "pld\t%a"},
-
- /* Intel Wireless MMX technology instructions. */
- #define FIRST_IWMMXT_INSN 0x0e130130
- #define IWMMXT_INSN_COUNT 47
- {0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
- {0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
- {0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
- {0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
- {0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
- {0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
- {0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
- {0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
- {0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
- {0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
- {0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
- {0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
- {0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
- {0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
- {0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
- {0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
- {0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
- {0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
- {0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
- {0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
- {0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
- {0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
- {0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
- {0x0e800100, 0x0fd00ff0, "wmadd%21?su%c\t%12-15g, %16-19g, %0-3g"},
- {0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%c\t%12-15g, %16-19g, %0-3g"},
- {0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
- {0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
- {0x0e300040, 0x0f300ff0, "wror%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
- {0x0e300148, 0x0f300ffc, "wror%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
- {0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
- {0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
- {0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
- {0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
- {0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
- {0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
- {0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
- {0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
- {0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
- {0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
- {0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
- {0x0e0000c0, 0x0f100fff, "wunpckeh%21?su%22-23w%c\t%12-15g, %16-19g"},
- {0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
- {0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
-
/* ARM V6 instructions. */
{0xfc500000, 0xfff00000, "mrrc2\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
{0xfc400000, 0xfff00000, "mcrr2\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
{0xf1080000, 0xfffdfe3f, "cpsie\t%8'a%7'i%6'f"},
{0xf1080000, 0xfffdfe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
--- 96,105 ----
*************** static const struct arm_opcode arm_opcod
*** 285,294 ****
--- 221,294 ----
{0x07800010, 0x0ff000f0, "usada8%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
{0x06e00010, 0x0fe00ff0, "usat%c\t%12-15r, #%16-20d, %0-3r"},
{0x06e00010, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, LSL #%7-11d"},
{0x06e00050, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, ASR #%7-11d"},
{0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15r, #%16-19d, %0-3r"},
+
+ /* V5J instruction. */
+ {0x012fff20, 0x0ffffff0, "bxj%c\t%0-3r"},
+
+ /* XScale instructions. */
+ {0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"},
+ {0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"},
+ {0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
+ {0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
+ {0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
+ {0xf450f000, 0xfc70f000, "pld\t%a"},
+
+ /* Intel Wireless MMX technology instructions. */
+ #define FIRST_IWMMXT_INSN 0x0e130130
+ #define IWMMXT_INSN_COUNT 47
+ {0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
+ {0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
+ {0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
+ {0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
+ {0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
+ {0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
+ {0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
+ {0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
+ {0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
+ {0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
+ {0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
+ {0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
+ {0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
+ {0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
+ {0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
+ {0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
+ {0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
+ {0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
+ {0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
+ {0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
+ {0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
+ {0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
+ {0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
+ {0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
+ {0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
+ {0x0e800100, 0x0fd00ff0, "wmadd%21?su%c\t%12-15g, %16-19g, %0-3g"},
+ {0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
+ {0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
+ {0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%c\t%12-15g, %16-19g, %0-3g"},
+ {0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
+ {0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
+ {0x0e300040, 0x0f300ff0, "wror%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
+ {0x0e300148, 0x0f300ffc, "wror%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
+ {0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
+ {0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
+ {0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
+ {0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
+ {0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
+ {0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
+ {0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
+ {0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
+ {0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
+ {0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
+ {0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
+ {0x0e0000c0, 0x0f100fff, "wunpckeh%21?su%22-23w%c\t%12-15g, %16-19g"},
+ {0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
+ {0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
+ {0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
+ {0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
/* V5 Instructions. */
{0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
{0xfa000000, 0xfe000000, "blx\t%B"},
{0x012fff30, 0x0ffffff0, "blx%c\t%0-3r"},
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