ppc440, dlmzb insn
Kumar Gala
kumar.gala@motorola.com
Tue Aug 19 14:53:00 GMT 2003
Alan,
Should the -m440 option be inclusive of 440GX features not in 440GP?
Look at IBM docs on the website I would recommend adding
PPC_OPCODE_RFMCI & PPC_OPCODE_ISEL to ppc_cpu.
- kumar
On Tuesday, August 19, 2003, at 01:44 AM, Alan Modra wrote:
>
> Thomas Cook wrote:
> [snip]
>> However, the dlmzb
>> instruction is not supported in the gnu binutils. This is a bit of
>> an embarrassment.
> [snip]
>> An interesting point that may help - the dlmbz instruction is
>> supported on
>> the 403, 405, and 440. (yes, the 403 is included here)
>
> The following adds the dlmzb instruction, and a -m440 option for
> gas.
>
> include/opcode/ChangeLog
> * ppc.h (PPC_OPCODE_440): Define. Formatting. Use hex for other
> PPC_OPCODE_* defines.
>
> opcodes/ChangeLog
> * ppc-opc.c (PPC440): Define.
> (powerpc_opcodes): Allow mac*, mul*, nmac*, dccci, dcread, iccci,
> icread instructions when PPC440. Add dlmzb instruction.
>
> gas/ChangeLog
> * config/tc-ppc.c (md_parse_option): Handle -m440.
> (md_apply_fix3): Warning fix.
> (md_show_usage): Add -m440.
> * doc/c-ppc.texi: Document -m440.
>
> Index: include/opcode/ppc.h
> ===================================================================
> RCS file: /cvs/src/src/include/opcode/ppc.h,v
> retrieving revision 1.15
> diff -u -p -r1.15 ppc.h
> --- include/opcode/ppc.h 7 Aug 2003 02:25:50 -0000 1.15
> +++ include/opcode/ppc.h 19 Aug 2003 06:17:08 -0000
> @@ -59,77 +59,80 @@ extern const int powerpc_num_opcodes;
> /* Values defined for the flags field of a struct powerpc_opcode. */
>
> /* Opcode is defined for the PowerPC architecture. */
> -#define PPC_OPCODE_PPC (01)
> +#define PPC_OPCODE_PPC 1
>
> /* Opcode is defined for the POWER (RS/6000) architecture. */
> -#define PPC_OPCODE_POWER (02)
> +#define PPC_OPCODE_POWER 2
>
> /* Opcode is defined for the POWER2 (Rios 2) architecture. */
> -#define PPC_OPCODE_POWER2 (04)
> +#define PPC_OPCODE_POWER2 4
>
> /* Opcode is only defined on 32 bit architectures. */
> -#define PPC_OPCODE_32 (010)
> +#define PPC_OPCODE_32 8
>
> /* Opcode is only defined on 64 bit architectures. */
> -#define PPC_OPCODE_64 (020)
> +#define PPC_OPCODE_64 0x10
>
> /* Opcode is supported by the Motorola PowerPC 601 processor. The 601
> is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
> but it also supports many additional POWER instructions. */
> -#define PPC_OPCODE_601 (040)
> +#define PPC_OPCODE_601 0x20
>
> /* Opcode is supported in both the Power and PowerPC architectures
> (ie, compiler's -mcpu=common or assembler's -mcom). */
> -#define PPC_OPCODE_COMMON (0100)
> +#define PPC_OPCODE_COMMON 0x40
>
> /* Opcode is supported for any Power or PowerPC platform (this is
> for the assembler's -many option, and it eliminates duplicates).
> */
> -#define PPC_OPCODE_ANY (0200)
> +#define PPC_OPCODE_ANY 0x80
>
> /* Opcode is supported as part of the 64-bit bridge. */
> -#define PPC_OPCODE_64_BRIDGE (0400)
> +#define PPC_OPCODE_64_BRIDGE 0x100
>
> /* Opcode is supported by Altivec Vector Unit */
> -#define PPC_OPCODE_ALTIVEC (01000)
> +#define PPC_OPCODE_ALTIVEC 0x200
>
> /* Opcode is supported by PowerPC 403 processor. */
> -#define PPC_OPCODE_403 (02000)
> +#define PPC_OPCODE_403 0x400
>
> /* Opcode is supported by PowerPC BookE processor. */
> -#define PPC_OPCODE_BOOKE (04000)
> +#define PPC_OPCODE_BOOKE 0x800
>
> /* Opcode is only supported by 64-bit PowerPC BookE processor. */
> -#define PPC_OPCODE_BOOKE64 (010000)
> +#define PPC_OPCODE_BOOKE64 0x1000
> +
> +/* Opcode is supported by PowerPC 440 processor. */
> +#define PPC_OPCODE_440 0x2000
>
> /* Opcode is only supported by Power4 architecture. */
> -#define PPC_OPCODE_POWER4 (020000)
> +#define PPC_OPCODE_POWER4 0x4000
>
> /* Opcode isn't supported by Power4 architecture. */
> -#define PPC_OPCODE_NOPOWER4 (040000)
> +#define PPC_OPCODE_NOPOWER4 0x8000
>
> /* Opcode is only supported by POWERPC Classic architecture. */
> -#define PPC_OPCODE_CLASSIC (0100000)
> +#define PPC_OPCODE_CLASSIC 0x10000
>
> /* Opcode is only supported by e500x2 Core. */
> -#define PPC_OPCODE_SPE (0200000)
> +#define PPC_OPCODE_SPE 0x20000
>
> /* Opcode is supported by e500x2 Integer select APU. */
> -#define PPC_OPCODE_ISEL (0400000)
> +#define PPC_OPCODE_ISEL 0x40000
>
> /* Opcode is an e500 SPE floating point instruction. */
> -#define PPC_OPCODE_EFS (01000000)
> +#define PPC_OPCODE_EFS 0x80000
>
> /* Opcode is supported by branch locking APU. */
> -#define PPC_OPCODE_BRLOCK (02000000)
> +#define PPC_OPCODE_BRLOCK 0x100000
>
> /* Opcode is supported by performance monitor APU. */
> -#define PPC_OPCODE_PMR (04000000)
> +#define PPC_OPCODE_PMR 0x200000
>
> /* Opcode is supported by cache locking APU. */
> -#define PPC_OPCODE_CACHELCK (010000000)
> +#define PPC_OPCODE_CACHELCK 0x400000
>
> /* Opcode is supported by machine check APU. */
> -#define PPC_OPCODE_RFMCI (020000000)
> +#define PPC_OPCODE_RFMCI 0x800000
>
> /* A macro to extract the major opcode from an instruction. */
> #define PPC_OP(i) (((i) >> 26) & 0x3f)
> Index: opcodes/ppc-opc.c
> ===================================================================
> RCS file: /cvs/src/src/opcodes/ppc-opc.c,v
> retrieving revision 1.54
> diff -u -p -r1.54 ppc-opc.c
> --- opcodes/ppc-opc.c 29 Jul 2003 08:29:56 -0000 1.54
> +++ opcodes/ppc-opc.c 19 Aug 2003 06:17:18 -0000
> @@ -1771,6 +1771,7 @@ extract_tbr (unsigned long insn,
> #define PPCONLY PPC_OPCODE_PPC
> #define PPC403 PPC_OPCODE_403
> #define PPC405 PPC403
> +#define PPC440 PPC_OPCODE_440
> #define PPC750 PPC
> #define PPC860 PPC
> #define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY | PPC_OPCODE_PPC
> @@ -1863,90 +1864,90 @@ const struct powerpc_opcode powerpc_opco
> { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
> { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
>
> -{ "macchw", XO(4,172,0,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "macchws", XO(4,236,0,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "machhw", XO(4,44,0,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "machhws", XO(4,108,0,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "mulchw", XRC(4,168,0), X_MASK, PPC405, { RT, RA, RB } },
> -{ "mulchw.", XRC(4,168,1), X_MASK, PPC405, { RT, RA, RB } },
> -{ "mulchwu", XRC(4,136,0), X_MASK, PPC405, { RT, RA, RB } },
> -{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405, { RT, RA, RB } },
> -{ "mulhhw", XRC(4,40,0), X_MASK, PPC405, { RT, RA, RB } },
> -{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405, { RT, RA, RB } },
> -{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405, { RT, RA, RB } },
> -{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405, { RT, RA, RB } },
> -{ "mullhw", XRC(4,424,0), X_MASK, PPC405, { RT, RA, RB } },
> -{ "mullhw.", XRC(4,424,1), X_MASK, PPC405, { RT, RA, RB } },
> -{ "mullhwu", XRC(4,392,0), X_MASK, PPC405, { RT, RA, RB } },
> -{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405, { RT, RA, RB } },
> -{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405, { RT, RA, RB } },
> -{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405, { RT, RA, RB } },
> +{ "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB }
> },
> +{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB }
> },
> +{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB }
> },
> +{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB }
> },
> +{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB }
> },
> +{ "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB }
> },
> +{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB }
> },
> +{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB }
> },
> +{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB }
> },
> +{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB }
> },
> +{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB }
> },
> +{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB }
> },
> +{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB }
> },
> +{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB }
> },
> +{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB }
> },
> +{ "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB }
> },
> +{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB }
> },
> +{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB }
> },
> +{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB }
> },
> +{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB }
> },
> +{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB }
> },
> +{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB }
> },
> +{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB }
> },
> +{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB }
> },
> +{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
> +{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB }
> },
> +{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB }
> },
> +{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB }
> },
> { "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
> { "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
> { "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
> @@ -3314,6 +3315,9 @@ const struct powerpc_opcode powerpc_opco
> { "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
> { "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
>
> +{ "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } },
> +{ "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } },
> +
> { "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
>
> { "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
> @@ -3783,7 +3787,7 @@ const struct powerpc_opcode powerpc_opco
> { "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
> { "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
>
> -{ "dccci", X(31,454), XRT_MASK, PPC403, { RA, RB } },
> +{ "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } },
>
> { "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
> { "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
> @@ -4065,7 +4069,7 @@ const struct powerpc_opcode powerpc_opco
>
> { "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
>
> -{ "dcread", X(31,486), X_MASK, PPC403, { RT, RA, RB }},
> +{ "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }},
>
> { "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
>
> @@ -4288,7 +4292,7 @@ const struct powerpc_opcode powerpc_opco
>
> { "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
>
> -{ "iccci", X(31,966), XRT_MASK, PPC403, { RA, RB } },
> +{ "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } },
>
> { "tlbwe", X(31,978), X_MASK, BOOKE, { 0 } },
>
> @@ -4305,7 +4309,7 @@ const struct powerpc_opcode powerpc_opco
> { "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } },
> { "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
>
> -{ "icread", X(31,998), XRT_MASK, PPC403, { RA, RB } },
> +{ "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } },
>
> { "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
> { "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA, RB } },
> Index: gas/config/tc-ppc.c
> ===================================================================
> RCS file: /cvs/src/src/gas/config/tc-ppc.c,v
> retrieving revision 1.79
> diff -u -p -r1.79 tc-ppc.c
> --- gas/config/tc-ppc.c 29 Jul 2003 06:48:30 -0000 1.79
> +++ gas/config/tc-ppc.c 19 Aug 2003 06:31:39 -0000
> @@ -910,6 +910,9 @@ md_parse_option (c, arg)
> || strcmp (arg, "405") == 0)
> ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC
> | PPC_OPCODE_403 | PPC_OPCODE_32);
> + else if (strcmp (arg, "440") == 0)
> + ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_32
> + | PPC_OPCODE_440);
> else if (strcmp (arg, "7400") == 0
> || strcmp (arg, "7410") == 0
> || strcmp (arg, "7450") == 0
> @@ -1074,6 +1077,7 @@ PowerPC options:\n\
> -mppc, -mppc32, -m603, -m604\n\
> generate code for PowerPC 603/604\n\
> -m403, -m405 generate code for PowerPC 403/405\n\
> +-m440 generate code for PowerPC 440\n\
> -m7400, -m7410, -m7450, -m7455\n\
> generate code For PowerPC 7400/7410/7450/7455\n"));
> fprintf (stream, _("\
> @@ -5733,7 +5737,7 @@ md_apply_fix3 (fixP, valP, seg)
> abort ();
> {
> unsigned char *where = fixP->fx_frag->fr_literal +
> fixP->fx_where;
> - long val, mask;
> + unsigned long val, mask;
>
> if (target_big_endian)
> val = bfd_getb32 (where - 2);
> Index: gas/doc/c-ppc.texi
> ===================================================================
> RCS file: /cvs/src/src/gas/doc/c-ppc.texi,v
> retrieving revision 1.2
> diff -u -p -r1.2 c-ppc.texi
> --- gas/doc/c-ppc.texi 25 Feb 2002 03:44:54 -0000 1.2
> +++ gas/doc/c-ppc.texi 19 Aug 2003 06:33:55 -0000
> @@ -48,6 +48,9 @@ Generate code for PowerPC 603/604.
> @item -m403, -m405
> Generate code for PowerPC 403/405.
>
> +@item -m440
> +Generate code for PowerPC 440. BookE and some 405 instructions.
> +
> @item -m7400, -m7410, -m7450, -m7455
> Generate code for PowerPC 7400/7410/7450/7455.
>
>
> --
> Alan Modra
> IBM OzLabs - Linux Technology Centre
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