[Patch] Add Intel syntax support for i860 (committed)
Jason Eckhardt
jle@owlnet.rice.edu
Sat Aug 2 03:08:00 GMT 2003
2003-08-01 Jason Eckhardt <jle@rice.edu>
* config/tc-i860.c: Remove SYNTAX_SVR4 macro and occurrences.
(target_intel_syntax): Declare variable.
(OPTION_INTEL_SYNTAX): Declare macro.
(md_longopts): Add option -mintel-syntax.
(md_parse_option): Set target_intel_syntax.
(md_show_usage): Add -mintel-syntax usage.
(md_begin): Set reg_prefix based on target_intel_syntax.
(i860_process_insn): Skip register prefix only if there is one.
Parse relocatable expressions in either Intel or AT&T syntax based
on target_intel_syntax instead of the SYNTAX_SVR4 macro.
* doc/c-i860.texi: Document -mintel-syntax option and give blurb
about the differences in syntax.
Index: config/tc-i860.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-i860.c,v
retrieving revision 1.18
diff -c -3 -p -r1.18 tc-i860.c
*** config/tc-i860.c 30 Jul 2003 20:24:55 -0000 1.18
--- config/tc-i860.c 2 Aug 2003 03:01:06 -0000
***************
*** 29,39 ****
#include "opcode/i860.h"
#include "elf/i860.h"
- /* Defined by default since this is primarily a SVR4/860 assembler.
- However, I'm trying to leave the door open for Intel syntax. Of course,
- if full support for anything other than SVR4 is done, then we should
- select this based on a command-line flag. */
- #define SYNTAX_SVR4
/* The opcode hash table. */
static struct hash_control *op_hash = NULL;
--- 29,34 ----
*************** const char EXP_CHARS[] = "eE";
*** 54,65 ****
As in 0f12.456 or 0d1.2345e12. */
const char FLT_CHARS[] = "rRsSfFdDxXpP";
! /* Register prefix. */
! #ifdef SYNTAX_SVR4
! static const char reg_prefix = '%';
! #else
! static const char reg_prefix = 0;
! #endif
#define MAX_FIXUPS 2
--- 49,56 ----
As in 0f12.456 or 0d1.2345e12. */
const char FLT_CHARS[] = "rRsSfFdDxXpP";
! /* Register prefix (depends on syntax). */
! static char reg_prefix;
#define MAX_FIXUPS 2
*************** static int target_warn_expand = 0;
*** 91,96 ****
--- 82,91 ----
/* If true, then XP support is enabled. */
static int target_xp = 0;
+ /* If true, then Intel syntax is enabled (default to AT&T/SVR4 syntax). */
+ static int target_intel_syntax = 0;
+
+
/* Prototypes. */
static void i860_process_insn (char *);
static void s_dual (int);
*************** md_begin (void)
*** 206,211 ****
--- 201,209 ----
if (lose)
as_fatal (_("Defective assembler. No assembly attempted."));
+
+ /* Set the register prefix for either Intel or AT&T/SVR4 syntax. */
+ reg_prefix = target_intel_syntax ? 0 : '%';
}
/* This is the core of the machine-dependent assembler. STR points to a
*************** i860_process_insn (char *str)
*** 524,530 ****
/* Check for register prefix if necessary. */
if (reg_prefix && *s != reg_prefix)
goto error;
! else
s++;
switch (*s)
--- 522,528 ----
/* Check for register prefix if necessary. */
if (reg_prefix && *s != reg_prefix)
goto error;
! else if (reg_prefix)
s++;
switch (*s)
*************** i860_process_insn (char *str)
*** 596,602 ****
/* Check for register prefix if necessary. */
if (reg_prefix && *s != reg_prefix)
goto error;
! else
s++;
if (*s++ == 'f' && ISDIGIT (*s))
--- 594,600 ----
/* Check for register prefix if necessary. */
if (reg_prefix && *s != reg_prefix)
goto error;
! else if (reg_prefix)
s++;
if (*s++ == 'f' && ISDIGIT (*s))
*************** i860_process_insn (char *str)
*** 645,651 ****
/* Check for register prefix if necessary. */
if (reg_prefix && *s != reg_prefix)
goto error;
! else
s++;
if (strncmp (s, "fir", 3) == 0)
--- 643,649 ----
/* Check for register prefix if necessary. */
if (reg_prefix && *s != reg_prefix)
goto error;
! else if (reg_prefix)
s++;
if (strncmp (s, "fir", 3) == 0)
*************** i860_process_insn (char *str)
*** 804,895 ****
SVR4 syntax. The Intel syntax is "ha%immediate"
whereas SVR4 syntax is "[immediate]@ha". */
immediate:
! #ifdef SYNTAX_SVR4
! if (*s == ' ')
! s++;
!
! /* Note that if i860_get_expression() fails, we will still
! have created U entries in the symbol table for the
! 'symbols' in the input string. Try not to create U
! symbols for registers, etc. */
! if (! i860_get_expression (s))
! s = expr_end;
! else
! goto error;
!
! if (strncmp (s, "@ha", 3) == 0)
! {
! the_insn.fi[fc].fup |= OP_SEL_HA;
! s += 3;
! }
! else if (strncmp (s, "@h", 2) == 0)
{
! the_insn.fi[fc].fup |= OP_SEL_H;
! s += 2;
! }
! else if (strncmp (s, "@l", 2) == 0)
! {
! the_insn.fi[fc].fup |= OP_SEL_L;
! s += 2;
! }
! else if (strncmp (s, "@gotoff", 7) == 0
! || strncmp (s, "@GOTOFF", 7) == 0)
! {
! as_bad (_("Assembler does not yet support PIC"));
! the_insn.fi[fc].fup |= OP_SEL_GOTOFF;
! s += 7;
! }
! else if (strncmp (s, "@got", 4) == 0
! || strncmp (s, "@GOT", 4) == 0)
! {
! as_bad (_("Assembler does not yet support PIC"));
! the_insn.fi[fc].fup |= OP_SEL_GOT;
! s += 4;
! }
! else if (strncmp (s, "@plt", 4) == 0
! || strncmp (s, "@PLT", 4) == 0)
! {
! as_bad (_("Assembler does not yet support PIC"));
! the_insn.fi[fc].fup |= OP_SEL_PLT;
! s += 4;
! }
! the_insn.expand = insn->expand;
! fc++;
! continue;
! #else /* ! SYNTAX_SVR4 */
! if (*s == ' ')
! s++;
! if (strncmp (s, "ha%", 3) == 0)
! {
! the_insn.fi[fc].fup |= OP_SEL_HA;
! s += 3;
! }
! else if (strncmp (s, "h%", 2) == 0)
! {
! the_insn.fi[fc].fup |= OP_SEL_H;
! s += 2;
}
! else if (strncmp (s, "l%", 2) == 0)
{
! the_insn.fi[fc].fup |= OP_SEL_L;
! s += 2;
! }
! the_insn.expand = insn->expand;
! /* Note that if i860_get_expression() fails, we will still
! have created U entries in the symbol table for the
! 'symbols' in the input string. Try not to create U
! symbols for registers, etc. */
! if (! i860_get_expression (s))
! s = expr_end;
! else
! goto error;
! fc++;
! continue;
! #endif /* SYNTAX_SVR4 */
break;
default:
--- 802,898 ----
SVR4 syntax. The Intel syntax is "ha%immediate"
whereas SVR4 syntax is "[immediate]@ha". */
immediate:
! if (target_intel_syntax == 0)
{
! /* AT&T/SVR4 syntax. */
! if (*s == ' ')
! s++;
!
! /* Note that if i860_get_expression() fails, we will still
! have created U entries in the symbol table for the
! 'symbols' in the input string. Try not to create U
! symbols for registers, etc. */
! if (! i860_get_expression (s))
! s = expr_end;
! else
! goto error;
! if (strncmp (s, "@ha", 3) == 0)
! {
! the_insn.fi[fc].fup |= OP_SEL_HA;
! s += 3;
! }
! else if (strncmp (s, "@h", 2) == 0)
! {
! the_insn.fi[fc].fup |= OP_SEL_H;
! s += 2;
! }
! else if (strncmp (s, "@l", 2) == 0)
! {
! the_insn.fi[fc].fup |= OP_SEL_L;
! s += 2;
! }
! else if (strncmp (s, "@gotoff", 7) == 0
! || strncmp (s, "@GOTOFF", 7) == 0)
! {
! as_bad (_("Assembler does not yet support PIC"));
! the_insn.fi[fc].fup |= OP_SEL_GOTOFF;
! s += 7;
! }
! else if (strncmp (s, "@got", 4) == 0
! || strncmp (s, "@GOT", 4) == 0)
! {
! as_bad (_("Assembler does not yet support PIC"));
! the_insn.fi[fc].fup |= OP_SEL_GOT;
! s += 4;
! }
! else if (strncmp (s, "@plt", 4) == 0
! || strncmp (s, "@PLT", 4) == 0)
! {
! as_bad (_("Assembler does not yet support PIC"));
! the_insn.fi[fc].fup |= OP_SEL_PLT;
! s += 4;
! }
!
! the_insn.expand = insn->expand;
! fc++;
! continue;
}
! else
{
! /* Intel syntax. */
! if (*s == ' ')
! s++;
! if (strncmp (s, "ha%", 3) == 0)
! {
! the_insn.fi[fc].fup |= OP_SEL_HA;
! s += 3;
! }
! else if (strncmp (s, "h%", 2) == 0)
! {
! the_insn.fi[fc].fup |= OP_SEL_H;
! s += 2;
! }
! else if (strncmp (s, "l%", 2) == 0)
! {
! the_insn.fi[fc].fup |= OP_SEL_L;
! s += 2;
! }
! the_insn.expand = insn->expand;
! /* Note that if i860_get_expression() fails, we will still
! have created U entries in the symbol table for the
! 'symbols' in the input string. Try not to create U
! symbols for registers, etc. */
! if (! i860_get_expression (s))
! s = expr_end;
! else
! goto error;
! fc++;
! continue;
! }
break;
default:
*************** const char *md_shortopts = "";
*** 1060,1071 ****
--- 1063,1076 ----
#define OPTION_EL (OPTION_MD_BASE + 1)
#define OPTION_WARN_EXPAND (OPTION_MD_BASE + 2)
#define OPTION_XP (OPTION_MD_BASE + 3)
+ #define OPTION_INTEL_SYNTAX (OPTION_MD_BASE + 4)
struct option md_longopts[] = {
{ "EB", no_argument, NULL, OPTION_EB },
{ "EL", no_argument, NULL, OPTION_EL },
{ "mwarn-expand", no_argument, NULL, OPTION_WARN_EXPAND },
{ "mxp", no_argument, NULL, OPTION_XP },
+ { "mintel-syntax",no_argument, NULL, OPTION_INTEL_SYNTAX },
{ NULL, no_argument, NULL, 0 }
};
size_t md_longopts_size = sizeof (md_longopts);
*************** md_parse_option (int c, char *arg ATTRIB
*** 1091,1096 ****
--- 1096,1105 ----
target_xp = 1;
break;
+ case OPTION_INTEL_SYNTAX:
+ target_intel_syntax = 1;
+ break;
+
#ifdef OBJ_ELF
/* SVR4 argument compatibility (-V): print version ID. */
case 'V':
*************** md_show_usage (FILE *stream)
*** 1117,1123 ****
-EL generate code for little endian mode (default)\n\
-EB generate code for big endian mode\n\
-mwarn-expand warn if pseudo operations are expanded\n\
! -mxp enable i860XP support (disabled by default)\n"));
#ifdef OBJ_ELF
/* SVR4 compatibility flags. */
fprintf (stream, _("\
--- 1126,1133 ----
-EL generate code for little endian mode (default)\n\
-EB generate code for big endian mode\n\
-mwarn-expand warn if pseudo operations are expanded\n\
! -mxp enable i860XP support (disabled by default)\n\
! -mintel-syntax enable Intel syntax (default to AT&T/SVR4)\n"));
#ifdef OBJ_ELF
/* SVR4 compatibility flags. */
fprintf (stream, _("\
Index: doc/c-i860.texi
===================================================================
RCS file: /cvs/src/src/gas/doc/c-i860.texi,v
retrieving revision 1.5
diff -c -3 -p -r1.5 c-i860.texi
*** doc/c-i860.texi 24 May 2003 04:22:22 -0000 1.5
--- doc/c-i860.texi 2 Aug 2003 03:01:06 -0000
***************
*** 13,22 ****
@ignore
@c FIXME: This is basically a stub for i860. There is tons more information
! that I will add later (jle@cygnus.com). The assembler is still being
! written. The i860 assembler that existed previously was never finished
! and doesn't even build. Further, its not BFD_ASSEMBLER and it doesn't
! do ELF (it doesn't do anything, but you get the point).
@end ignore
@cindex i860 support
--- 13,19 ----
@ignore
@c FIXME: This is basically a stub for i860. There is tons more information
! that I will add later (jle@cygnus.com).
@end ignore
@cindex i860 support
*************** support SVR4 PIC (i.e., @code{@@GOT, @@G
*** 36,41 ****
--- 33,45 ----
Like the SVR4/860 assembler, the output object format is ELF32. Currently,
this is the only supported object format. If there is sufficient interest,
other formats such as COFF may be implemented.
+
+ Both the Intel and AT&T/SVR4 syntaxes are supported, with the latter
+ being the default. One difference is that AT&T syntax requires the '%'
+ prefix on register names while Intel syntax does not. Another difference
+ is in the specification of relocatable expressions. The Intel syntax
+ is @code{ha%expression} whereas the SVR4 syntax is @code{[expression]@@ha}
+ (and similarly for the "l" and "h" selectors).
@node Options-i860
@section i860 Command-line Options
@subsection SVR4 compatibility options
*************** where @code{gcc} may emit these pseudo-i
*** 66,71 ****
--- 70,78 ----
Enable support for the i860XP instructions and control registers. By default,
this option is disabled so that only the base instruction set (i.e., i860XR)
is supported.
+ @item -mintel-syntax
+ The i860 assembler defaults to AT&T/SVR4 syntax. This option enables the
+ Intel syntax.
@end table
@node Directives-i860
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