Patch to add support for more NEC VR targets [bfd]

Richard Sandiford rsandifo@redhat.com
Fri Sep 27 09:54:00 GMT 2002


The patch below adds vr4120, vr5400 and vr5500 MIPS targets to bfd.
Perhaps the only noteworthy thing is that we allow vr5400 code to be
linked to vr5500 code, and treated as vr5500 code, even though the
vr5400 has a multimedia extension that the vr5500 doesn't.  See the
comment in _bfd_mips_elf_mach_extends_p.

Tested on mips64-elf.  OK to install?

Richard

2002-09-27  Gavin Romig-Koch  <gavin@redhat.com>
            Ken Raeburn  <raeburn@cygnus.com>
            Aldy Hernandez  <aldyh@redhat.com>
            Eric Christopher  <echristo@redhat.com>
            Richard Sandiford  <rsandifo@redhat.com>

[include/elf]
	* mips.h (E_MIPS_MACH_4120, E_MIPS_MACH_5400, E_MIPS_MACH_5500): New.

[bfd/]
	* archures.c (bfd_mach_mips4120, bfd_mach_mips5400): New.
	(bfd_mach_mips5500): New.
	* cpu-mips.c (I_mips4120, I_mips5400, I_mips5500): New.
	(arch_info_struct): Add corresponding entries here.
	* elfxx-mips.c (_bfd_elf_mips_mach): Handle E_MIPS_MACH_4120,
	E_MIPS_MACH_5400 and E_MIPS_MACH_5500.
	(_bfd_mips_elf_final_write_processing): Handle bfd_mach_mips4120,
	bfd_mach_mips5400 and bfd_mach_mips5500.
	(_bfd_mips_elf_mach_extends_p): New function.
	(_bfd_mips_elf_merge_private_bfd_data): Use it to help merge
	the EF_MIPS_MACH flags.
	
Index: include/elf/mips.h
===================================================================
RCS file: /cvs/src/src/include/elf/mips.h,v
retrieving revision 1.16
diff -c -d -p -r1.16 mips.h
*** include/elf/mips.h	31 Aug 2001 21:21:54 -0000	1.16
--- include/elf/mips.h	27 Sep 2002 13:41:18 -0000
*************** END_RELOC_NUMBERS (R_MIPS_maxext)
*** 175,182 ****
--- 175,185 ----
  #define E_MIPS_MACH_4010	0x00820000
  #define E_MIPS_MACH_4100	0x00830000
  #define E_MIPS_MACH_4650	0x00850000
+ #define E_MIPS_MACH_4120	0x00870000
  #define E_MIPS_MACH_4111	0x00880000
  #define E_MIPS_MACH_SB1         0x008a0000
+ #define E_MIPS_MACH_5400	0x00910000
+ #define E_MIPS_MACH_5500	0x00980000
  
  /* Processor specific section indices.  These sections do not actually
     exist.  Symbols with a st_shndx field corresponding to one of these
Index: bfd/archures.c
===================================================================
RCS file: /cvs/src/src/bfd/archures.c,v
retrieving revision 1.55
diff -c -d -p -r1.55 archures.c
*** bfd/archures.c	29 Aug 2002 06:49:33 -0000	1.55
--- bfd/archures.c	27 Sep 2002 13:41:18 -0000
*************** DESCRIPTION
*** 129,139 ****
--- 129,142 ----
  .#define bfd_mach_mips4010		4010
  .#define bfd_mach_mips4100		4100
  .#define bfd_mach_mips4111		4111
+ .#define bfd_mach_mips4120		4120
  .#define bfd_mach_mips4300		4300
  .#define bfd_mach_mips4400		4400
  .#define bfd_mach_mips4600		4600
  .#define bfd_mach_mips4650		4650
  .#define bfd_mach_mips5000		5000
+ .#define bfd_mach_mips5400		5400
+ .#define bfd_mach_mips5500		5500
  .#define bfd_mach_mips6000		6000
  .#define bfd_mach_mips8000		8000
  .#define bfd_mach_mips10000		10000
Index: bfd/cpu-mips.c
===================================================================
RCS file: /cvs/src/src/bfd/cpu-mips.c,v
retrieving revision 1.14
diff -c -d -p -r1.14 cpu-mips.c
*** bfd/cpu-mips.c	19 May 2002 21:06:34 -0000	1.14
--- bfd/cpu-mips.c	27 Sep 2002 13:41:18 -0000
*************** enum
*** 67,77 ****
--- 67,80 ----
    I_mips4010,
    I_mips4100,
    I_mips4111,
+   I_mips4120,
    I_mips4300,
    I_mips4400,
    I_mips4600,
    I_mips4650,
    I_mips5000,
+   I_mips5400,
+   I_mips5500,
    I_mips6000,
    I_mips8000,
    I_mips10000,
*************** static const bfd_arch_info_type arch_inf
*** 93,103 ****
--- 96,109 ----
    N (64, 64, bfd_mach_mips4010, "mips:4010",      false, NN(I_mips4010)),
    N (64, 64, bfd_mach_mips4100, "mips:4100",      false, NN(I_mips4100)),
    N (64, 64, bfd_mach_mips4111, "mips:4111",      false, NN(I_mips4111)),
+   N (64, 64, bfd_mach_mips4120, "mips:4120",      false, NN(I_mips4120)),
    N (64, 64, bfd_mach_mips4300, "mips:4300",      false, NN(I_mips4300)),
    N (64, 64, bfd_mach_mips4400, "mips:4400",      false, NN(I_mips4400)),
    N (64, 64, bfd_mach_mips4600, "mips:4600",      false, NN(I_mips4600)),
    N (64, 64, bfd_mach_mips4650, "mips:4650",      false, NN(I_mips4650)),
    N (64, 64, bfd_mach_mips5000, "mips:5000",      false, NN(I_mips5000)),
+   N (64, 64, bfd_mach_mips5400, "mips:5400",      false, NN(I_mips5400)),
+   N (64, 64, bfd_mach_mips5500, "mips:5500",      false, NN(I_mips5500)),
    N (32, 32, bfd_mach_mips6000, "mips:6000",      false, NN(I_mips6000)),
    N (64, 64, bfd_mach_mips8000, "mips:8000",      false, NN(I_mips8000)),
    N (64, 64, bfd_mach_mips10000,"mips:10000",     false, NN(I_mips10000)),
Index: bfd/elfxx-mips.c
===================================================================
RCS file: /cvs/src/src/bfd/elfxx-mips.c,v
retrieving revision 1.23
diff -c -d -p -r1.23 elfxx-mips.c
*** bfd/elfxx-mips.c	26 Sep 2002 09:10:57 -0000	1.23
--- bfd/elfxx-mips.c	27 Sep 2002 13:41:18 -0000
*************** static INLINE int elf_mips_isa PARAMS ((
*** 364,369 ****
--- 364,370 ----
  static INLINE char* elf_mips_abi_name PARAMS ((bfd *));
  static void mips_elf_irix6_finish_dynamic_symbol
    PARAMS ((bfd *, const char *, Elf_Internal_Sym *));
+ static boolean _bfd_mips_elf_mach_extends_p PARAMS ((flagword, flagword));
  
  /* This will be used when we sort the dynamic relocation records.  */
  static bfd *reldyn_sorting_bfd;
*************** _bfd_elf_mips_mach (flags)
*** 3058,3066 ****
--- 3059,3076 ----
      case E_MIPS_MACH_4111:
        return bfd_mach_mips4111;
  
+     case E_MIPS_MACH_4120:
+       return bfd_mach_mips4120;
+ 
      case E_MIPS_MACH_4650:
        return bfd_mach_mips4650;
  
+     case E_MIPS_MACH_5400:
+       return bfd_mach_mips5400;
+ 
+     case E_MIPS_MACH_5500:
+       return bfd_mach_mips5500;
+ 
      case E_MIPS_MACH_SB1:
        return bfd_mach_mips_sb1;
  
*************** _bfd_mips_elf_final_write_processing (ab
*** 5935,5944 ****
--- 5945,5966 ----
        val = E_MIPS_ARCH_3 | E_MIPS_MACH_4111;
        break;
  
+     case bfd_mach_mips4120:
+       val = E_MIPS_ARCH_3 | E_MIPS_MACH_4120;
+       break;
+ 
      case bfd_mach_mips4650:
        val = E_MIPS_ARCH_3 | E_MIPS_MACH_4650;
        break;
  
+     case bfd_mach_mips5400:
+       val = E_MIPS_ARCH_4 | E_MIPS_MACH_5400;
+       break;
+ 
+     case bfd_mach_mips5500:
+       val = E_MIPS_ARCH_4 | E_MIPS_MACH_5500;
+       break;
+ 
      case bfd_mach_mips5000:
      case bfd_mach_mips8000:
      case bfd_mach_mips10000:
*************** _bfd_mips_elf_final_link (abfd, info)
*** 7637,7642 ****
--- 7659,7684 ----
    return true;
  }
  
+ /* Return true if machine EXTENSION is an extension of machine BASE,
+    meaning that it should be safe to link code for the two machines
+    and set the output machine to EXTENSION.  EXTENSION and BASE are
+    both submasks of EF_MIPS_MACH.  */
+ 
+ static boolean
+ _bfd_mips_elf_mach_extends_p (base, extension)
+      flagword base, extension;
+ {
+   /* The vr5500 ISA is an extension of the core vr5400 ISA, but doesn't
+      include the multimedia stuff.  It seems better to allow vr5400
+      and vr5500 code to be merged anyway, since many libraries will
+      just use the core ISA.  Perhaps we could add some sort of ASE
+      flag if this ever proves a problem.  */
+   return (base == 0
+ 	  || (base == E_MIPS_MACH_5400 && extension == E_MIPS_MACH_5500)
+ 	  || (base == E_MIPS_MACH_4100 && extension == E_MIPS_MACH_4111)
+ 	  || (base == E_MIPS_MACH_4100 && extension == E_MIPS_MACH_4120));
+ }
+ 
  /* Merge backend specific data from an object file to the output
     object file when linking.  */
  
*************** _bfd_mips_elf_merge_private_bfd_data (ib
*** 7743,7752 ****
  
        /* If either has no machine specified, just compare the general isa's.
  	 Some combinations of machines are ok, if the isa's match.  */
!       if (! new_mach
! 	  || ! old_mach
! 	  || new_mach == old_mach
! 	  )
  	{
  	  /* Don't warn about mixing code using 32-bit ISAs, or mixing code
  	     using 64-bit ISAs.  They will normally use the same data sizes
--- 7785,7793 ----
  
        /* If either has no machine specified, just compare the general isa's.
  	 Some combinations of machines are ok, if the isa's match.  */
!       if (new_mach == old_mach
! 	  || _bfd_mips_elf_mach_extends_p (new_mach, old_mach)
! 	  || _bfd_mips_elf_mach_extends_p (old_mach, new_mach))
  	{
  	  /* Don't warn about mixing code using 32-bit ISAs, or mixing code
  	     using 64-bit ISAs.  They will normally use the same data sizes
*************** _bfd_mips_elf_merge_private_bfd_data (ib
*** 7763,7770 ****
  	  else
  	    {
  	      /* Do we need to update the mach field?  */
! 	      if (old_mach == 0 && new_mach != 0) 
! 		elf_elfheader (obfd)->e_flags |= new_mach;
  
  	      /* Do we need to update the ISA field?  */
  	      if (new_isa > old_isa)
--- 7804,7814 ----
  	  else
  	    {
  	      /* Do we need to update the mach field?  */
! 	      if (_bfd_mips_elf_mach_extends_p (old_mach, new_mach))
! 		{
! 		  elf_elfheader (obfd)->e_flags &= ~EF_MIPS_MACH;
! 		  elf_elfheader (obfd)->e_flags |= new_mach;
! 		}
  
  	      /* Do we need to update the ISA field?  */
  	      if (new_isa > old_isa)



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