[MIPS PATCH RFA] Add SB-1 MDMX support.
cgd@broadcom.com
cgd@broadcom.com
Thu May 30 23:46:00 GMT 2002
ChangeLog and testsuite entries tell the story. 8-)
Tested by building binutils & running binutils make check for mips-elf,
mips64-elf, mipsisa32-elf, host x86-linux.
chris
===================================================================
[ opcodes/ChangeLog ]
2002-05-31 Chris G. Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* mips-opc.c: Add support for SB-1 MDMX subset and extensions.
[ gas/testsuite/ChangeLog ]
2002-05-31 Chris G. Demetriou <cgd@broadcom.com>
* gas/mips/sb1-ext-mdmx.s: New file.
* gas/mips/sb1-ext-mdmx.d: Likewise.
* gas/mips/mips.exp: Run new "sb1-ext-mdmx" test.
Index: gas/testsuite/gas/mips/sb1-ext-mdmx.s
===================================================================
RCS file: gas/testsuite/gas/mips/sb1-ext-mdmx.s
diff -N gas/testsuite/gas/mips/sb1-ext-mdmx.s
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/sb1-ext-mdmx.s 31 May 2002 06:41:19 -0000
@@ -0,0 +1,169 @@
+# Source file to test assembly of SB-1 MDMX subset instructions and extensions.
+#
+# SB-1 implements only the .ob MDMX instructions, and adds three additional
+# MDMX-ish instructions (pabsdiff, pabsdiffc, pavg).
+
+ .set noreorder
+ .set noat
+
+ .globl text_label .text
+text_label:
+
+ # The normal MDMX instructions:
+
+ movf.l $v1, $v12, $fcc5
+
+ movn.l $v1, $v12, $18
+
+ movt.l $v1, $v12, $fcc5
+
+ movz.l $v1, $v12, $18
+
+ add.ob $v1, $v12, 18
+ add.ob $v1, $v12, $v18
+ add.ob $v1, $v12, $v18[6]
+
+ adda.ob $v12, 18
+ adda.ob $v12, $v18
+ adda.ob $v12, $v18[6]
+
+ addl.ob $v12, 18
+ addl.ob $v12, $v18
+ addl.ob $v12, $v18[6]
+
+ alni.ob $v1, $v12, $v18, 6
+
+ alnv.ob $v1, $v12, $v18, $21
+
+ and.ob $v1, $v12, 18
+ and.ob $v1, $v12, $v18
+ and.ob $v1, $v12, $v18[6]
+
+ c.eq.ob $v12, 18
+ c.eq.ob $v12, $v18
+ c.eq.ob $v12, $v18[6]
+
+ c.le.ob $v12, 18
+ c.le.ob $v12, $v18
+ c.le.ob $v12, $v18[6]
+
+ c.lt.ob $v12, 18
+ c.lt.ob $v12, $v18
+ c.lt.ob $v12, $v18[6]
+
+ max.ob $v1, $v12, 18
+ max.ob $v1, $v12, $v18
+ max.ob $v1, $v12, $v18[6]
+
+ min.ob $v1, $v12, 18
+ min.ob $v1, $v12, $v18
+ min.ob $v1, $v12, $v18[6]
+
+ mul.ob $v1, $v12, 18
+ mul.ob $v1, $v12, $v18
+ mul.ob $v1, $v12, $v18[6]
+
+ mula.ob $v12, 18
+ mula.ob $v12, $v18
+ mula.ob $v12, $v18[6]
+
+ mull.ob $v12, 18
+ mull.ob $v12, $v18
+ mull.ob $v12, $v18[6]
+
+ muls.ob $v12, 18
+ muls.ob $v12, $v18
+ muls.ob $v12, $v18[6]
+
+ mulsl.ob $v12, 18
+ mulsl.ob $v12, $v18
+ mulsl.ob $v12, $v18[6]
+
+ nor.ob $v1, $v12, 18
+ nor.ob $v1, $v12, $v18
+ nor.ob $v1, $v12, $v18[6]
+
+ or.ob $v1, $v12, 18
+ or.ob $v1, $v12, $v18
+ or.ob $v1, $v12, $v18[6]
+
+ pickf.ob $v1, $v12, 18
+ pickf.ob $v1, $v12, $v18
+ pickf.ob $v1, $v12, $v18[6]
+
+ pickt.ob $v1, $v12, 18
+ pickt.ob $v1, $v12, $v18
+ pickt.ob $v1, $v12, $v18[6]
+
+ rach.ob $v1
+
+ racl.ob $v1
+
+ racm.ob $v1
+
+ rnau.ob $v1, 18
+ rnau.ob $v1, $v18
+ rnau.ob $v1, $v18[6]
+
+ rneu.ob $v1, 18
+ rneu.ob $v1, $v18
+ rneu.ob $v1, $v18[6]
+
+ rzu.ob $v1, 18
+ rzu.ob $v1, $v18
+ rzu.ob $v1, $v18[6]
+
+ shfl.mixh.ob $v1, $v12, $v18
+
+ shfl.mixl.ob $v1, $v12, $v18
+
+ shfl.pach.ob $v1, $v12, $v18
+
+ shfl.upsl.ob $v1, $v12, $v18
+
+ sll.ob $v1, $v12, 18
+ sll.ob $v1, $v12, $v18
+ sll.ob $v1, $v12, $v18[6]
+
+ srl.ob $v1, $v12, 18
+ srl.ob $v1, $v12, $v18
+ srl.ob $v1, $v12, $v18[6]
+
+ sub.ob $v1, $v12, 18
+ sub.ob $v1, $v12, $v18
+ sub.ob $v1, $v12, $v18[6]
+
+ suba.ob $v12, 18
+ suba.ob $v12, $v18
+ suba.ob $v12, $v18[6]
+
+ subl.ob $v12, 18
+ subl.ob $v12, $v18
+ subl.ob $v12, $v18[6]
+
+ wach.ob $v12
+
+ wacl.ob $v12, $v18
+
+ xor.ob $v1, $v12, 18
+ xor.ob $v1, $v12, $v18
+ xor.ob $v1, $v12, $v18[6]
+
+
+ # The extensions:
+
+ pabsdiff.ob $v1, $v12, 18
+ pabsdiff.ob $v1, $v12, $v18
+ pabsdiff.ob $v1, $v12, $v18[6]
+
+ pabsdiffc.ob $v12, 18
+ pabsdiffc.ob $v12, $v18
+ pabsdiffc.ob $v12, $v18[6]
+
+ pavg.ob $v1, $v12, 18
+ pavg.ob $v1, $v12, $v18
+ pavg.ob $v1, $v12, $v18[6]
+
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .space 8
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.34
diff -u -p -r1.34 mips.exp
--- gas/testsuite/gas/mips/mips.exp 31 May 2002 01:17:17 -0000 1.34
+++ gas/testsuite/gas/mips/mips.exp 31 May 2002 06:41:19 -0000
@@ -153,6 +153,7 @@ if { [istarget mips*-*-*] } then {
run_dump_test "mips64"
run_dump_test "mips64-mips3d"
run_dump_test "mips64-mdmx"
+ run_dump_test "sb1-ext-mdmx"
run_dump_test "sb1-ext-ps"
# It will always fail until someone fixes it.
Index: gas/testsuite/gas/mips/sb1-ext-mdmx.d
===================================================================
RCS file: gas/testsuite/gas/mips/sb1-ext-mdmx.d
diff -N gas/testsuite/gas/mips/sb1-ext-mdmx.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/sb1-ext-mdmx.d 31 May 2002 06:41:19 -0000
@@ -0,0 +1,115 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -mmips:sb1
+#name: SB-1 MDMX subset and extensions
+#as: -march=sb1
+
+# Check SB-1 MDMX subset and extensions assembly and disassembly
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 46b46051 movf\.l \$f1,\$f12,\$fcc5
+0+0004 <[^>]*> 46b26053 movn\.l \$f1,\$f12,s2
+0+0008 <[^>]*> 46b56051 movt\.l \$f1,\$f12,\$fcc5
+0+000c <[^>]*> 46b26052 movz\.l \$f1,\$f12,s2
+0+0010 <[^>]*> 7bd2604b add\.ob \$v1,\$v12,0x12
+0+0014 <[^>]*> 7ad2604b add\.ob \$v1,\$v12,\$v18
+0+0018 <[^>]*> 7992604b add\.ob \$v1,\$v12,\$v18\[6\]
+0+001c <[^>]*> 7bd26037 adda\.ob \$v12,0x12
+0+0020 <[^>]*> 7ad26037 adda\.ob \$v12,\$v18
+0+0024 <[^>]*> 79926037 adda\.ob \$v12,\$v18\[6\]
+0+0028 <[^>]*> 7bd26437 addl\.ob \$v12,0x12
+0+002c <[^>]*> 7ad26437 addl\.ob \$v12,\$v18
+0+0030 <[^>]*> 79926437 addl\.ob \$v12,\$v18\[6\]
+0+0034 <[^>]*> 78d26058 alni\.ob \$v1,\$v12,\$v18,6
+0+0038 <[^>]*> 7ab26059 alnv\.ob \$v1,\$v12,\$v18,s5
+0+003c <[^>]*> 7bd2604c and\.ob \$v1,\$v12,0x12
+0+0040 <[^>]*> 7ad2604c and\.ob \$v1,\$v12,\$v18
+0+0044 <[^>]*> 7992604c and\.ob \$v1,\$v12,\$v18\[6\]
+0+0048 <[^>]*> 7bd26001 c\.eq\.ob \$v12,0x12
+0+004c <[^>]*> 7ad26001 c\.eq\.ob \$v12,\$v18
+0+0050 <[^>]*> 79926001 c\.eq\.ob \$v12,\$v18\[6\]
+0+0054 <[^>]*> 7bd26005 c\.le\.ob \$v12,0x12
+0+0058 <[^>]*> 7ad26005 c\.le\.ob \$v12,\$v18
+0+005c <[^>]*> 79926005 c\.le\.ob \$v12,\$v18\[6\]
+0+0060 <[^>]*> 7bd26004 c\.lt\.ob \$v12,0x12
+0+0064 <[^>]*> 7ad26004 c\.lt\.ob \$v12,\$v18
+0+0068 <[^>]*> 79926004 c\.lt\.ob \$v12,\$v18\[6\]
+0+006c <[^>]*> 7bd26047 max\.ob \$v1,\$v12,0x12
+0+0070 <[^>]*> 7ad26047 max\.ob \$v1,\$v12,\$v18
+0+0074 <[^>]*> 79926047 max\.ob \$v1,\$v12,\$v18\[6\]
+0+0078 <[^>]*> 7bd26046 min\.ob \$v1,\$v12,0x12
+0+007c <[^>]*> 7ad26046 min\.ob \$v1,\$v12,\$v18
+0+0080 <[^>]*> 79926046 min\.ob \$v1,\$v12,\$v18\[6\]
+0+0084 <[^>]*> 7bd26070 mul\.ob \$v1,\$v12,0x12
+0+0088 <[^>]*> 7ad26070 mul\.ob \$v1,\$v12,\$v18
+0+008c <[^>]*> 79926070 mul\.ob \$v1,\$v12,\$v18\[6\]
+0+0090 <[^>]*> 7bd26033 mula\.ob \$v12,0x12
+0+0094 <[^>]*> 7ad26033 mula\.ob \$v12,\$v18
+0+0098 <[^>]*> 79926033 mula\.ob \$v12,\$v18\[6\]
+0+009c <[^>]*> 7bd26433 mull\.ob \$v12,0x12
+0+00a0 <[^>]*> 7ad26433 mull\.ob \$v12,\$v18
+0+00a4 <[^>]*> 79926433 mull\.ob \$v12,\$v18\[6\]
+0+00a8 <[^>]*> 7bd26032 muls\.ob \$v12,0x12
+0+00ac <[^>]*> 7ad26032 muls\.ob \$v12,\$v18
+0+00b0 <[^>]*> 79926032 muls\.ob \$v12,\$v18\[6\]
+0+00b4 <[^>]*> 7bd26432 mulsl\.ob \$v12,0x12
+0+00b8 <[^>]*> 7ad26432 mulsl\.ob \$v12,\$v18
+0+00bc <[^>]*> 79926432 mulsl\.ob \$v12,\$v18\[6\]
+0+00c0 <[^>]*> 7bd2604f nor\.ob \$v1,\$v12,0x12
+0+00c4 <[^>]*> 7ad2604f nor\.ob \$v1,\$v12,\$v18
+0+00c8 <[^>]*> 7992604f nor\.ob \$v1,\$v12,\$v18\[6\]
+0+00cc <[^>]*> 7bd2604e or\.ob \$v1,\$v12,0x12
+0+00d0 <[^>]*> 7ad2604e or\.ob \$v1,\$v12,\$v18
+0+00d4 <[^>]*> 7992604e or\.ob \$v1,\$v12,\$v18\[6\]
+0+00d8 <[^>]*> 7bd26042 pickf\.ob \$v1,\$v12,0x12
+0+00dc <[^>]*> 7ad26042 pickf\.ob \$v1,\$v12,\$v18
+0+00e0 <[^>]*> 79926042 pickf\.ob \$v1,\$v12,\$v18\[6\]
+0+00e4 <[^>]*> 7bd26043 pickt\.ob \$v1,\$v12,0x12
+0+00e8 <[^>]*> 7ad26043 pickt\.ob \$v1,\$v12,\$v18
+0+00ec <[^>]*> 79926043 pickt\.ob \$v1,\$v12,\$v18\[6\]
+0+00f0 <[^>]*> 7a00007f rach\.ob \$v1
+0+00f4 <[^>]*> 7800007f racl\.ob \$v1
+0+00f8 <[^>]*> 7900007f racm\.ob \$v1
+0+00fc <[^>]*> 7bd20061 rnau\.ob \$v1,0x12
+0+0100 <[^>]*> 7ad20061 rnau\.ob \$v1,\$v18
+0+0104 <[^>]*> 79920061 rnau\.ob \$v1,\$v18\[6\]
+0+0108 <[^>]*> 7bd20062 rneu\.ob \$v1,0x12
+0+010c <[^>]*> 7ad20062 rneu\.ob \$v1,\$v18
+0+0110 <[^>]*> 79920062 rneu\.ob \$v1,\$v18\[6\]
+0+0114 <[^>]*> 7bd20060 rzu\.ob \$v1,0x12
+0+0118 <[^>]*> 7ad20060 rzu\.ob \$v1,\$v18
+0+011c <[^>]*> 79920060 rzu\.ob \$v1,\$v18\[6\]
+0+0120 <[^>]*> 7992605f shfl\.mixh\.ob \$v1,\$v12,\$v18
+0+0124 <[^>]*> 79d2605f shfl\.mixl\.ob \$v1,\$v12,\$v18
+0+0128 <[^>]*> 7912605f shfl\.pach\.ob \$v1,\$v12,\$v18
+0+012c <[^>]*> 78d2605f shfl\.upsl\.ob \$v1,\$v12,\$v18
+0+0130 <[^>]*> 7bd26050 sll\.ob \$v1,\$v12,0x12
+0+0134 <[^>]*> 7ad26050 sll\.ob \$v1,\$v12,\$v18
+0+0138 <[^>]*> 79926050 sll\.ob \$v1,\$v12,\$v18\[6\]
+0+013c <[^>]*> 7bd26052 srl\.ob \$v1,\$v12,0x12
+0+0140 <[^>]*> 7ad26052 srl\.ob \$v1,\$v12,\$v18
+0+0144 <[^>]*> 79926052 srl\.ob \$v1,\$v12,\$v18\[6\]
+0+0148 <[^>]*> 7bd2604a sub\.ob \$v1,\$v12,0x12
+0+014c <[^>]*> 7ad2604a sub\.ob \$v1,\$v12,\$v18
+0+0150 <[^>]*> 7992604a sub\.ob \$v1,\$v12,\$v18\[6\]
+0+0154 <[^>]*> 7bd26036 suba\.ob \$v12,0x12
+0+0158 <[^>]*> 7ad26036 suba\.ob \$v12,\$v18
+0+015c <[^>]*> 79926036 suba\.ob \$v12,\$v18\[6\]
+0+0160 <[^>]*> 7bd26436 subl\.ob \$v12,0x12
+0+0164 <[^>]*> 7ad26436 subl\.ob \$v12,\$v18
+0+0168 <[^>]*> 79926436 subl\.ob \$v12,\$v18\[6\]
+0+016c <[^>]*> 7a00603e wach\.ob \$v12
+0+0170 <[^>]*> 7812603e wacl\.ob \$v12,\$v18
+0+0174 <[^>]*> 7bd2604d xor\.ob \$v1,\$v12,0x12
+0+0178 <[^>]*> 7ad2604d xor\.ob \$v1,\$v12,\$v18
+0+017c <[^>]*> 7992604d xor\.ob \$v1,\$v12,\$v18\[6\]
+0+0180 <[^>]*> 7bd26049 pabsdiff\.ob \$v1,\$v12,0x12
+0+0184 <[^>]*> 7ad26049 pabsdiff\.ob \$v1,\$v12,\$v18
+0+0188 <[^>]*> 79926049 pabsdiff\.ob \$v1,\$v12,\$v18\[6\]
+0+018c <[^>]*> 7bd26035 pabsdiffc\.ob \$v12,0x12
+0+0190 <[^>]*> 7ad26035 pabsdiffc\.ob \$v12,\$v18
+0+0194 <[^>]*> 79926035 pabsdiffc\.ob \$v12,\$v18\[6\]
+0+0198 <[^>]*> 7bd26048 pavg\.ob \$v1,\$v12,0x12
+0+019c <[^>]*> 7ad26048 pavg\.ob \$v1,\$v12,\$v18
+0+01a0 <[^>]*> 79926048 pavg\.ob \$v1,\$v12,\$v18\[6\]
+ \.\.\.
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.34
diff -u -p -r1.34 mips-opc.c
--- opcodes/mips-opc.c 31 May 2002 01:17:18 -0000 1.34
+++ opcodes/mips-opc.c 31 May 2002 06:41:23 -0000
@@ -150,26 +150,26 @@ const struct mips_opcode mips_builtin_op
{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, I1 },
{"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
{"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
-{"add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
+{"add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
{"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
{"add.qh", "X,Y,Q", 0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
-{"adda.ob", "Y,Q", 0x78000037, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
+{"adda.ob", "Y,Q", 0x78000037, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 },
{"adda.qh", "Y,Q", 0x78200037, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
{"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, I1 },
{"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, I1 },
-{"addl.ob", "Y,Q", 0x78000437, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
+{"addl.ob", "Y,Q", 0x78000437, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 },
{"addl.qh", "Y,Q", 0x78200437, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
{"addr.ps", "D,S,T", 0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, M3D },
{"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, I1 },
-{"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D, MX },
+{"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
{"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D, MX },
{"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D, I5 },
-{"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, MX },
+{"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, MX|SB1 },
{"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, MX },
{"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, I1 },
-{"and.ob", "X,Y,Q", 0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
+{"and.ob", "X,Y,Q", 0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
{"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, I1 },
/* b is at the top of the table. */
@@ -274,7 +274,7 @@ const struct mips_opcode mips_builtin_op
{"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
{"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
{"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
-{"c.eq.ob", "Y,Q", 0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX },
+{"c.eq.ob", "Y,Q", 0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX|SB1 },
{"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.eq.qh", "Y,Q", 0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX },
@@ -336,7 +336,7 @@ const struct mips_opcode mips_builtin_op
{"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
{"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
{"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
-{"c.lt.ob", "Y,Q", 0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX },
+{"c.lt.ob", "Y,Q", 0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX|SB1 },
{"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.lt.qh", "Y,Q", 0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX },
@@ -350,7 +350,7 @@ const struct mips_opcode mips_builtin_op
{"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
{"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
{"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
-{"c.le.ob", "Y,Q", 0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX },
+{"c.le.ob", "Y,Q", 0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX|SB1 },
{"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.le.qh", "Y,Q", 0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX },
@@ -650,7 +650,7 @@ const struct mips_opcode mips_builtin_op
{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, G1 },
{"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 },
{"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, V1 },
-{"max.ob", "X,Y,Q", 0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
+{"max.ob", "X,Y,Q", 0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
{"max.qh", "X,Y,Q", 0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
{"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0, M1 },
{"mfps", "t,P", 0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0, M1 },
@@ -664,35 +664,35 @@ const struct mips_opcode mips_builtin_op
{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, I32 },
{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, I1 },
{"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, I1 },
-{"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
+{"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
{"min.qh", "X,Y,Q", 0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
{"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, I1 },
{"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, I1 },
{"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, I5 },
{"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_D|FP_S, I4|I32},
{"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4|I32 },
-{"movf.l", "D,S,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, MX },
-{"movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, MX },
+{"movf.l", "D,S,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, MX|SB1 },
+{"movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, MX|SB1 },
{"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4|I32 },
{"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I5 },
{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, I4|I32 },
{"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, L1 },
{"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4|I32 },
-{"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, MX },
-{"movn.l", "X,Y,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, MX },
+{"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, MX|SB1 },
+{"movn.l", "X,Y,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, MX|SB1 },
{"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4|I32 },
{"movn.ps", "D,S,t", 0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I5 },
{"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC, I4|I32 },
{"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4|I32 },
-{"movt.l", "D,S,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, MX },
-{"movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, MX },
+{"movt.l", "D,S,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, MX|SB1 },
+{"movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, MX|SB1 },
{"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4|I32 },
{"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I5 },
{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, I4|I32 },
{"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, L1 },
{"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4|I32 },
-{"movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, MX },
-{"movz.l", "X,Y,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, MX },
+{"movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, MX|SB1 },
+{"movz.l", "X,Y,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, MX|SB1 },
{"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4|I32 },
{"movz.ps", "D,S,t", 0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I5 },
/* move is at the top of the table. */
@@ -718,24 +718,24 @@ const struct mips_opcode mips_builtin_op
{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, I1 },
{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
{"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
-{"mul.ob", "X,Y,Q", 0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
+{"mul.ob", "X,Y,Q", 0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
{"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
{"mul.qh", "X,Y,Q", 0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
{"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, I32|P3 },
{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, I1 },
{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, I1 },
-{"mula.ob", "Y,Q", 0x78000033, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
+{"mula.ob", "Y,Q", 0x78000033, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 },
{"mula.qh", "Y,Q", 0x78200033, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
-{"mull.ob", "Y,Q", 0x78000433, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
+{"mull.ob", "Y,Q", 0x78000433, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 },
{"mull.qh", "Y,Q", 0x78200433, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, I1 },
{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, I1 },
{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, I1 },
{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, I1 },
{"mulr.ps", "D,S,T", 0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, M3D },
-{"muls.ob", "Y,Q", 0x78000032, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
+{"muls.ob", "Y,Q", 0x78000032, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 },
{"muls.qh", "Y,Q", 0x78200032, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
-{"mulsl.ob", "Y,Q", 0x78000432, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
+{"mulsl.ob", "Y,Q", 0x78000432, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 },
{"mulsl.qh", "Y,Q", 0x78200432, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
{"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, I1 },
{"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 },
@@ -755,28 +755,31 @@ const struct mips_opcode mips_builtin_op
/* nop is at the start of the table. */
{"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
{"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, I1 },
-{"nor.ob", "X,Y,Q", 0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
+{"nor.ob", "X,Y,Q", 0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
{"nor.qh", "X,Y,Q", 0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
{"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, I1 },/*nor d,s,0*/
{"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, I1 },
-{"or.ob", "X,Y,Q", 0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
+{"or.ob", "X,Y,Q", 0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
{"or.qh", "X,Y,Q", 0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
{"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, I1 },
-{"pickf.ob", "X,Y,Q", 0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
+{"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, SB1 },
+{"pabsdiffc.ob", "Y,Q", 0x78000035, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, SB1 },
+{"pavg.ob", "X,Y,Q", 0x78000008, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, SB1 },
+{"pickf.ob", "X,Y,Q", 0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
{"pickf.qh", "X,Y,Q", 0x78200002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
-{"pickt.ob", "X,Y,Q", 0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
+{"pickt.ob", "X,Y,Q", 0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
{"pickt.qh", "X,Y,Q", 0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
{"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
{"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
/* pref and prefx are at the start of the table. */
{"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
{"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
-{"rach.ob", "X", 0x7a00003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX },
+{"rach.ob", "X", 0x7a00003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX|SB1 },
{"rach.qh", "X", 0x7a20003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX },
-{"racl.ob", "X", 0x7800003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX },
+{"racl.ob", "X", 0x7800003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX|SB1 },
{"racl.qh", "X", 0x7820003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX },
-{"racm.ob", "X", 0x7900003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX },
+{"racm.ob", "X", 0x7900003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX|SB1 },
{"racm.qh", "X", 0x7920003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX },
{"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, I4 },
{"recip.ps","D,S", 0x46c00015, 0xffff003f, WR_D|RD_S|FP_D, SB1 },
@@ -795,10 +798,10 @@ const struct mips_opcode mips_builtin_op
{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, I1 },
{"rfe", "", 0x42000010, 0xffffffff, 0, I1|T3 },
{"rnas.qh", "X,Q", 0x78200025, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX },
-{"rnau.ob", "X,Q", 0x78000021, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX },
+{"rnau.ob", "X,Q", 0x78000021, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX|SB1 },
{"rnau.qh", "X,Q", 0x78200021, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX },
{"rnes.qh", "X,Q", 0x78200026, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX },
-{"rneu.ob", "X,Q", 0x78000022, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX },
+{"rneu.ob", "X,Q", 0x78000022, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX|SB1 },
{"rneu.qh", "X,Q", 0x78200022, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX },
{"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, I1 },
{"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, I1 },
@@ -818,7 +821,7 @@ const struct mips_opcode mips_builtin_op
{"rsqrt2.ps", "D,S,T", 0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D },
{"rsqrt2.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D },
{"rzs.qh", "X,Q", 0x78200024, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX },
-{"rzu.ob", "X,Q", 0x78000020, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX },
+{"rzu.ob", "X,Q", 0x78000020, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX|SB1 },
{"rzu.qh", "X,Q", 0x78200020, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX },
{"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, I1 },
{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, I1 },
@@ -865,15 +868,15 @@ const struct mips_opcode mips_builtin_op
{"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, I1 },
{"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, I1 },
{"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX },
-{"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX },
+{"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
{"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX },
-{"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX },
+{"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
{"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX },
-{"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX },
+{"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
{"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX },
{"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX },
{"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX },
-{"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX },
+{"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
{"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, I1 },
{"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, I1 },
{"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, I1 },
@@ -881,7 +884,7 @@ const struct mips_opcode mips_builtin_op
{"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, I1 },
{"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* sllv */
{"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, I1 },
-{"sll.ob", "X,Y,Q", 0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
+{"sll.ob", "X,Y,Q", 0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
{"sll.qh", "X,Y,Q", 0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
{"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
{"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, I1 },
@@ -901,7 +904,7 @@ const struct mips_opcode mips_builtin_op
{"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 },
{"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srlv */
{"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, I1 },
-{"srl.ob", "X,Y,Q", 0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
+{"srl.ob", "X,Y,Q", 0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
{"srl.qh", "X,Y,Q", 0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
/* ssnop is at the start of the table. */
{"standby", "", 0x42000021, 0xffffffff, 0, V1 },
@@ -909,12 +912,12 @@ const struct mips_opcode mips_builtin_op
{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, I1 },
{"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
{"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
-{"sub.ob", "X,Y,Q", 0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
+{"sub.ob", "X,Y,Q", 0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
{"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
{"sub.qh", "X,Y,Q", 0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
-{"suba.ob", "Y,Q", 0x78000036, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
+{"suba.ob", "Y,Q", 0x78000036, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 },
{"suba.qh", "Y,Q", 0x78200036, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
-{"subl.ob", "Y,Q", 0x78000436, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
+{"subl.ob", "Y,Q", 0x78000436, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 },
{"subl.qh", "Y,Q", 0x78200436, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
{"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
{"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, I1 },
@@ -1006,12 +1009,12 @@ const struct mips_opcode mips_builtin_op
{"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, I1 },
{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, I1 },
-{"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
+{"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
{"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, I1 },
-{"wach.ob", "Y", 0x7a00003e, 0xffff07ff, WR_MACC|RD_S|FP_D, MX },
+{"wach.ob", "Y", 0x7a00003e, 0xffff07ff, WR_MACC|RD_S|FP_D, MX|SB1 },
{"wach.qh", "Y", 0x7a20003e, 0xffff07ff, WR_MACC|RD_S|FP_D, MX },
-{"wacl.ob", "Y,Z", 0x7800003e, 0xffe007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
+{"wacl.ob", "Y,Z", 0x7800003e, 0xffe007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 },
{"wacl.qh", "Y,Z", 0x7820003e, 0xffe007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
{"wait", "", 0x42000020, 0xffffffff, TRAP, I3|I32 },
{"wait", "J", 0x42000020, 0xfe00003f, TRAP, I32 },
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