[PATCH] Better handling of MIPS16 instructions

[Thiemo Seufer]

Hi All,

this adds some/better handling of MIPS16 instructions. For now, this
affects only jalx.


Thiemo


2002-06-12  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>

	/gas/ChangeLog
	* config/tc-mips.c (macro_build): Handle MIPS16 insns.
	(mips_ip): Likewise.

	/include/opcode/ChangeLog
	* mips.h (INSN_MIPS16): New define.

	/opcodes/ChangeLog
	* mips-dis.c (mips_isa_type): Add MIPS16 insn handling.
	* mips-opc.c (I16): New define.
	(mips_builtin_opcodes): Make jalx an I16 insn.


diff -BurpNX /bigdisk/src/binutils-exclude source-orig/gas/config/tc-mips.c source/gas/config/tc-mips.c
--- source-orig/gas/config/tc-mips.c	Fri Jun  7 02:38:45 2002
+++ source/gas/config/tc-mips.c	Fri Jun  7 06:47:17 2002
@@ -2705,7 +2722,10 @@ macro_build (place, counter, ep, name, f
          MDMX or MIPS-3D instructions.  */
       if (strcmp (fmt, insn.insn_mo->args) == 0
 	  && insn.insn_mo->pinfo != INSN_MACRO
-	  && OPCODE_IS_MEMBER (insn.insn_mo, mips_opts.isa, mips_arch)
+  	  && OPCODE_IS_MEMBER (insn.insn_mo,
+  			       (mips_opts.isa
+	      		        | (mips_opts.mips16 ? INSN_MIPS16 : 0)),
+			       mips_arch)
 	  && (mips_arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
 	break;
 
@@ -7708,6 +7726,7 @@ mips_ip (str, ip)
 
       if (OPCODE_IS_MEMBER (insn,
 			    (mips_opts.isa
+			     | (mips_opts.mips16 ? INSN_MIPS16 : 0)
 	      		     | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
 			     | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
 			    mips_arch))
diff -BurpNX /bigdisk/src/binutils-exclude source-orig/include/opcode/mips.h source/include/opcode/mips.h
--- source-orig/include/opcode/mips.h	Fri May 31 20:28:42 2002
+++ source/include/opcode/mips.h	Mon Jun  3 23:51:37 2002
@@ -339,7 +339,10 @@ struct mips_opcode
 #define INSN_ISA64                0x00000400
 
 /* Masks used for MIPS-defined ASEs.  */
+#define INSN_ASE_MASK		  0x0000f000
 
+/* MIPS 16 ASE */
+#define INSN_MIPS16               0x00002000
 /* MIPS-3D ASE */
 #define INSN_MIPS3D               0x00004000
 /* MDMX ASE */ 
diff -BurpNX /bigdisk/src/binutils-exclude source-orig/opcodes/mips-dis.c source/opcodes/mips-dis.c
--- source-orig/opcodes/mips-dis.c	Fri May 31 20:30:06 2002
+++ source/opcodes/mips-dis.c	Mon Jun  3 23:50:27 2002
@@ -412,7 +412,7 @@ mips_isa_type (mach, isa, cputype)
       break;
     case bfd_mach_mips16:
       *cputype = CPU_MIPS16;
-      *isa = ISA_MIPS3;
+      *isa = ISA_MIPS3 | INSN_MIPS16;
       break;
     case bfd_mach_mips5:
       *cputype = CPU_MIPS5;
@@ -429,12 +429,12 @@ mips_isa_type (mach, isa, cputype)
 	 _MIPS32 Architecture For Programmers Volume I: Introduction to the
 	 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
 	 page 1.  */
-      *isa = ISA_MIPS32;
+      *isa = ISA_MIPS32 | INSN_MIPS16;
       break;
     case bfd_mach_mipsisa64:
       *cputype = CPU_MIPS64;
       /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs.  */
-      *isa = ISA_MIPS64 | INSN_MDMX | INSN_MIPS3D;
+      *isa = ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX;
       break;
 
     default:
diff -BurpNX /bigdisk/src/binutils-exclude source-orig/opcodes/mips-opc.c source/opcodes/mips-opc.c
--- source-orig/opcodes/mips-opc.c	Sat Jun  1 02:27:14 2002
+++ source/opcodes/mips-opc.c	Tue Jun  4 02:44:19 2002
@@ -87,6 +87,9 @@ Software Foundation, 59 Temple Place - S
 #define I64     INSN_ISA64
 
 /* MIPS64 MIPS-3D ASE support.  */
+#define I16     INSN_MIPS16
+
+/* MIPS64 MIPS-3D ASE support.  */
 #define M3D     INSN_MIPS3D
 
 /* MIPS64 MDMX ASE support.  */
@@ -568,9 +571,7 @@ const struct mips_opcode mips_builtin_op
    assembler, but will never match user input (because the line above
    will match first).  */
 {"jal",     "a",	0x0c000000, 0xfc000000,	UBD|WR_31,		I1	},
-  /* jalx really should only be avaliable if mips16 is available,
-     but for now make it I1. */
-{"jalx",    "a",	0x74000000, 0xfc000000, UBD|WR_31,		I1      },
+{"jalx",    "a",	0x74000000, 0xfc000000, UBD|WR_31,		I16     },
 {"la",      "t,o(b)",	0x24000000, 0xfc000000,	WR_t|RD_s,		I1	}, /* addiu */
 {"la",      "t,A(b)",	0,    (int) M_LA_AB,	INSN_MACRO,		I1	},
 {"lb",      "t,o(b)",	0x80000000, 0xfc000000,	LDD|RD_b|WR_t,		I1	},