[ PATCH] : SH Assembler generates incorrect opcode for PCMP instructions

[Arati Dikey]

Hi !

The SH assembler generates incorrect opcodes for the parallel PCMP
instruction.
Basically, its last nibble is a copy of the previous instruction's
second nibble
when working in Big Endian format.

For example,
test.s
	movs.w @-R5, A0
      PCMP X0,Y0

 generates opcodes
	f5 70
	f8 00 84 05

 instead of
	f8 00 84 00

The following patch corrects this. I have also verified that it does not
cause any
side effect on other DSP instructions.

Regards,
Arati Dikey



--- tc-sh.c.orig	Thu Dec  6 11:34:18 2001
+++ tc-sh.c	      Thu Jan 17 16:41:28 2002
@@ -1769,7 +1769,10 @@
 	  if (field_b)
 	    as_bad (_("multiple parallel processing specifications"));
 	  field_b = ((opcode->nibbles[2] << 12) + (opcode->nibbles[3] <<
8)
-		     + (reg_x << 6) + (reg_y << 4) + reg_n);
+		     + (reg_x << 6) + (reg_y << 4) );
+
+	  if (strcmp (opcode->name, "pcmp") != 0)
+	  	 field_b += reg_n;
 	  break;
 	case PDC:
 	  if (cond)