[PATCH]: Support linker relaxation for 68HC11

[Stephane Carrez]

Hi!

This patch adds support for linker relaxation for 68HC11.
When the address is within 0..0x0ff, we can use a direct addressing
mode for some instruction and reduce them by having a 1 byte address (instead of 2).
(big portions of code taken from existing targets).

Committed on mainline.

	Stephane

2002-08-14  Stephane Carrez  <stcarrez@nerim.fr>

	* elf32-m68hc11.c (m68hc11_relax_group): New to relax group of
	instructions.
	(m68hc11_direct_relax): New to define table of relaxable instructions.
	(find_relaxable_insn): New, find a relaxable insn.
	(compare_reloc): New to compare two relocs.
	(m68hc11_elf_relax_section): New, relax text sections.
	(m68hc11_elf_relax_delete_bytes): New, delete bytes and adjust branchs.
	(elf32_m68hc11_check_relocs): New function for GC support.
	(elf32_m68hc11_relocate_section): New function for GC support.
	(bfd_elf32_bfd_relax_section): Define to support linker relaxation.
	(elf_backend_check_relocs): Likewise.
	(elf_backend_relocate_section): Likewise.
-------------- next part --------------
An embedded and charset-unspecified text was scrubbed...
Name: bfd.diffs
URL: <https://sourceware.org/pipermail/binutils/attachments/20020814/dac6306f/attachment.ksh>