BookE cleanup & AltiVec patch.
matthew green
mrg@cygnus.com
Wed Oct 17 03:35:00 GMT 2001
hi folks.
the following patch:
- cleans up a BookE include/opcodes/ppc.h typo
- adds some missing -moptions
- add support for the 6 missing altivec instructions (including
the beginnings of an altivec testsuite.)
- fixes altivec `mtvscr' operand list
OK to commit?
thanks,
.mrg.
[gas]
2001-10-17 matthew green <mrg@redhat.com>
* config/tc-ppc.c (md_show_usage): Add missing -maltivec, -m7400,
-m7410, -m7450 and -m7455 options.
[gas/testsuite]
2001-10-17 matthew green <mrg@redhat.com>
* gas/ppc/altivec.s: New test for AltiVec.
* gas/ppc/altivec.d: New file.
* gas/ppc/ppc.exp: Test altivec.s
[include/opcode]
2001-10-17 matthew green <mrg@redhat.com>
* ppc.h (PPC_OPCODE_BOOKE64): Fix typo.
[opcodes]
2001-10-17 matthew green <mrg@redhat.com>
* ppc-opc.c (STRM): New AltiVec operand.
(XDSS): New AltiVec instruction form.
(mtvscr): Correct operand list.
(dst, dstt, dstst, dststt, dss, dssall): AltiVec instructions.
Index: gas/config/tc-ppc.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-ppc.c,v
retrieving revision 1.37
diff -p -r1.37 tc-ppc.c
*** tc-ppc.c 2001/10/17 06:03:41 1.37
--- tc-ppc.c 2001/10/17 10:11:02
*************** PowerPC options:\n\
*** 1028,1037 ****
-mppc, -mppc32, -m603, -m604\n\
generate code for Motorola PowerPC 603/604\n\
-m403, -m405 generate code for Motorola PowerPC 403/405\n\
-mppc64, -m620 generate code for Motorola PowerPC 620\n\
-mppc64bridge generate code for PowerPC 64, including bridge insns\n\
! -mbooke64 generate code for 64-bit Motorola BookE\n\
! -mbooke, mbooke32 generate code for 32-bit Motorola BookE\n\
-mcom generate code Power/PowerPC common instructions\n\
-many generate code for any architecture (PWR/PWRX/PPC)\n\
-mregnames Allow symbolic names for registers\n\
--- 1028,1040 ----
-mppc, -mppc32, -m603, -m604\n\
generate code for Motorola PowerPC 603/604\n\
-m403, -m405 generate code for Motorola PowerPC 403/405\n\
+ -m7400, -m7410, -m7450, -m7455\n\
+ generate code For Motorola PowerPC 7400/7410/7450/7455\n\
-mppc64, -m620 generate code for Motorola PowerPC 620\n\
-mppc64bridge generate code for PowerPC 64, including bridge insns\n\
! -mbooke64 generate code for 64-bit Motorola BookE\n\
! -mbooke, mbooke32 generate code for 32-bit Motorola BookE\n\
! -maltivec generate code for AltiVec\n\
-mcom generate code Power/PowerPC common instructions\n\
-many generate code for any architecture (PWR/PWRX/PPC)\n\
-mregnames Allow symbolic names for registers\n\
Index: gas/testsuite/gas/ppc/altivec.d
===================================================================
RCS file: altivec.d
diff -N altivec.d
*** /dev/null Tue May 5 13:32:27 1998
--- altivec.d Wed Oct 17 03:11:05 2001
***************
*** 0 ****
--- 1,16 ----
+ #as: -m601 -maltivec
+ #objdump: -Dr
+ #name: AltiVec tests
+
+ .*: +file format elf32-powerpc
+
+ Disassembly of section \.text:
+
+ 00000000 <start>:
+ 0: 7c 60 06 6c dss 3
+ 4: 7e 40 06 6c dssall 2
+ 8: 7c 25 22 ac dst r5,r4,1
+ c: 7e 08 3a ac dstt r8,r7,0
+ 10: 7c 65 32 ec dstst r5,r6,3
+ 14: 7e 44 2a ec dststt r4,r5,2
+ Disassembly of section \.data:
Index: gas/testsuite/gas/ppc/altivec.s
===================================================================
RCS file: altivec.s
diff -N altivec.s
*** /dev/null Tue May 5 13:32:27 1998
--- altivec.s Wed Oct 17 03:11:05 2001
***************
*** 0 ****
--- 1,10 ----
+ # PowerPC AltiVec tests
+ #as: -m601 -maltivec
+ .section ".text"
+ start:
+ dss 3
+ dssall 2
+ dst 5,4,1
+ dstt 8,7,0
+ dstst 5,6,3
+ dststt 4,5,2
Index: gas/testsuite/gas/ppc/ppc.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/ppc/ppc.exp,v
retrieving revision 1.3
diff -p -r1.3 ppc.exp
*** ppc.exp 2001/10/13 01:59:09 1.3
--- ppc.exp 2001/10/17 10:11:05
*************** if { [istarget powerpc64*-*-*] || [istar
*** 27,30 ****
--- 27,31 ----
if { [istarget powerpc*-*-*] } then {
run_dump_test "simpshft"
run_dump_test "booke"
+ run_dump_test "altivec"
}
Index: include/opcode/ppc.h
===================================================================
RCS file: /cvs/src/src/include/opcode/ppc.h,v
retrieving revision 1.8
diff -p -r1.8 ppc.h
*** ppc.h 2001/10/13 01:59:09 1.8
--- ppc.h 2001/10/17 10:11:08
*************** extern const int powerpc_num_opcodes;
*** 98,104 ****
#define PPC_OPCODE_BOOKE (04000)
/* Opcode is only supported by 64-bit Motorola BookE processor. */
! #define PPC_OPCODE_BOOKE64 (001000)
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
--- 98,104 ----
#define PPC_OPCODE_BOOKE (04000)
/* Opcode is only supported by 64-bit Motorola BookE processor. */
! #define PPC_OPCODE_BOOKE64 (010000)
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
Index: opcodes/ppc-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-opc.c,v
retrieving revision 1.20
diff -p -r1.20 ppc-opc.c
*** ppc-opc.c 2001/10/14 01:19:09 1.20
--- ppc-opc.c 2001/10/17 10:11:11
*************** const struct powerpc_operand powerpc_ope
*** 403,410 ****
#define SR SPRG + 1
{ 4, 16, 0, 0, 0 },
/* The SV field in a POWER SC form instruction. */
! #define SV SR + 1
{ 14, 2, 0, 0, 0 },
/* The TBR field in an XFX form instruction. This is like the SPR
--- 403,415 ----
#define SR SPRG + 1
{ 4, 16, 0, 0, 0 },
+ /* The STRM frield in an X AltiVec form instruction. */
+ #define STRM SR + 1
+ #define STRM_MASK (0x3 << 21)
+ { 2, 21, 0, 0, 0 },
+
/* The SV field in a POWER SC form instruction. */
! #define SV STRM + 1
{ 14, 2, 0, 0, 0 },
/* The TBR field in an XFX form instruction. This is like the SPR
*************** extract_tbr (insn, invalid)
*** 1289,1294 ****
--- 1294,1303 ----
/* An X form sync instruction with everything filled in except the LS field. */
#define XSYNC_MASK (0xff9fffff)
+ /* An X form AltiVec dss instruction. */
+ #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
+ #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
+
/* An XFL form instruction. */
#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
*************** const struct powerpc_opcode powerpc_opco
*** 1584,1590 ****
{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405, { RT, RA, RB } },
{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405, { RT, RA, RB } },
{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
! { "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VD } },
{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
{ "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
{ "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
--- 1593,1599 ----
{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405, { RT, RA, RB } },
{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405, { RT, RA, RB } },
{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
! { "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
{ "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
{ "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
*************** const struct powerpc_opcode powerpc_opco
*** 2972,2981 ****
--- 2981,2996 ----
{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA, RB } },
+ { "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
+ { "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
+
{ "lhax", X(31,343), X_MASK, COM, { RT, RA, RB } },
{ "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA, RB } },
+ { "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
+ { "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
+
{ "dccci", X(31,454), XRT_MASK, PPC403, { RA, RB } },
{ "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
*************** const struct powerpc_opcode powerpc_opco
*** 3365,3370 ****
--- 3380,3388 ----
{ "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA, RB } },
{ "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
+
+ { "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } },
+ { "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { STRM } },
{ "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
{ "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
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