motorola booke opcodes/gas support
matthew green
mrg@cygnus.com
Wed Oct 10 21:36:00 GMT 2001
hi folks.
the follow set of patches implement the motorola booke extensions
for gas and the disassembler.
i had to modify some previous behaviour, specifically to make PPC403
support first class and not simply part of "PPC", and in the opcodes
table, both PPC403 and PPC64 no longer include PPC_OPCODE_ANY. this
is because these processors conflict with the BookE in about a dozen
instructions all up.
i've modified the -m403/-m405 switches to gas accordingly, as well as
adding a few more CPU variants (-m74{10,50,55}), a new -maltivec to just
enable altivec support, and new -mbooke{,32} options. to cope with
disassembly, i've extended the powerpc disassembler to take note of,
eg, `objdump -d -M booke' (disassemble_info{}->disassembler_options).
i have also included is a testsuite for the new booke instructions.
OK to commit?
.mrg.
[gas/ChangeLog]
2001-10-11 matthew green <mrg@redhat.com>
* config/tc-ppc.c (md_parse_option): New -m7410, -m7450 and -m7455
flags, equivalent to -m7400. New -maltivec to enable AltiVec
instructions. New -mbooke and -mbooke32 flags to enable 64-bit
and 32-bit BookE support, respectively. Change -m403 and -m405 to
set PPC403 option.
(md_show_usage): Adjust for new options.
[gas/testsuite/ChangeLog]
2001-10-11 matthew green <mrg@redhat.com>
* gas/ppc/booke.s: New test for Motorola BookE.
* gas/ppc/booke.d: New file.
* gas/ppc/ppc.exp: Test booke.s.
[include/opcode/ChangeLog]
2001-10-11 matthew green <mrg@redhat.com>
* ppc.h (PPC_OPCODE_BOOKE, PPC_OPCODE_403): New opcode flags for
BookE and PowerPC403 instructions.
[opcodes/ChangeLog]
2001-10-11 matthew green <mrg@redhat.com>
* ppc-opc.c (insert_de, extract_de, insert_des, extract_des): New
instruction field instruction/extraction functions for new BookE
DE form instructions.
(CT): New macro for CT field in an X form instruction.
(DE, DES, DEO, DE_MASK): New macros for DE/DES fields in DE form
instructions.
(PPC64): Don't include PPC_OPCODE_PPC.
(403): New opcode macro for PPC403 processors.
(BOOKE): New opcode macro for BookE processors.
(bce, bcel, bcea, bcela, bclre, bclrel: New BookE instructions.
(bcctre, bcctrel, be, bel, bea, bela, icbt, icbte, lwzxe): Likewise.
(dcbste, lwzuxe, luxe, dcbfe, lbzxe, lwarxe, lbzuxe): Likewise.
(stwcxe, stwxe, stxe, stwuxe, stuxe, stbxe, dcbtste, stbuxe): Likewise.
(mfapidi, dcbte, lhzxe, lhzuxe, lhaxe, lhauxe, subfe64): Likewise.
(subfeo64, adde64, addeo64, sthxe, sthuxe, subfze64): Likewise.
(subfzeo64, addze64, addzeo64, dcbie, subfme64, subfmeo64): Likewise.
(addme64, addmeo64, stdcxe., mcrxr64, lwbrxe, lfsxe, lfsuxe): Likewise.
(lfdxe, lfdxue, stwbrxe, stfsxe, stfsxue, stfdxe, dcbae): Likewise.
(stfdxue, tlbivax, tlbivaxe, lhbrxe, ldxe, ldxue, tlbsx): Likewise.
(tlbsxe, sthbrxe, stdxe, stdxue, icbie, stfiwxe, dcbze, lbze): Likewise.
(lbzue, ldue, lhze, lhzue, lhae, lhaue, lwze, lwzue): Likewise.
(stbe, stbue, sthe, sthue, stwe, stwue, lfse, lfsue, lfde): Likewise.
(lfdue, stde, stdue, stfse, stfsue, stfde, stfdue): Likewise.
* ppc-dis.c (print_insn_big_powerpc, print_insn_little_powerpc): Look
for a disassembler option of `booke' or `booke32' to enable BookE
support in the disassembler.
Index: gas/config/tc-ppc.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-ppc.c,v
retrieving revision 1.35
diff -p -r1.35 tc-ppc.c
*** tc-ppc.c 2001/10/08 18:14:43 1.35
--- tc-ppc.c 2001/10/11 04:23:47
*************** md_parse_option (c, arg)
*** 887,911 ****
Motorola PowerPC 603/604. */
else if (strcmp (arg, "ppc") == 0
|| strcmp (arg, "ppc32") == 0
- || strcmp (arg, "403") == 0
- || strcmp (arg, "405") == 0
|| strcmp (arg, "603") == 0
|| strcmp (arg, "604") == 0)
ppc_cpu = PPC_OPCODE_PPC;
! else if (strcmp (arg, "7400") == 0)
ppc_cpu = PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC;
/* -mppc64 and -m620 mean to assemble for the 64-bit PowerPC
620. */
else if (strcmp (arg, "ppc64") == 0 || strcmp (arg, "620") == 0)
{
! ppc_cpu = PPC_OPCODE_PPC;
ppc_size = PPC_OPCODE_64;
}
else if (strcmp (arg, "ppc64bridge") == 0)
{
! ppc_cpu = PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE;
ppc_size = PPC_OPCODE_64;
}
/* -mcom means assemble for the common intersection between Power
and PowerPC. At present, we just allow the union, rather
than the intersection. */
--- 887,927 ----
Motorola PowerPC 603/604. */
else if (strcmp (arg, "ppc") == 0
|| strcmp (arg, "ppc32") == 0
|| strcmp (arg, "603") == 0
|| strcmp (arg, "604") == 0)
ppc_cpu = PPC_OPCODE_PPC;
! /* -m403 and -m405 mean to assemble for the Motorola PowerPC 403/405. */
! else if (strcmp (arg, "403") == 0
! || strcmp (arg, "405") == 0)
! ppc_cpu = PPC_OPCODE_PPC | PPC_OPCODE_403;
! else if (strcmp (arg, "7400") == 0
! || strcmp (arg, "7410") == 0
! || strcmp (arg, "7450") == 0
! || strcmp (arg, "7455") == 0)
ppc_cpu = PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC;
+ else if (strcmp (arg, "altivec") == 0)
+ ppc_cpu |= PPC_OPCODE_ALTIVEC;
/* -mppc64 and -m620 mean to assemble for the 64-bit PowerPC
620. */
else if (strcmp (arg, "ppc64") == 0 || strcmp (arg, "620") == 0)
{
! ppc_cpu = PPC_OPCODE_PPC | PPC_OPCODE_64;
ppc_size = PPC_OPCODE_64;
}
else if (strcmp (arg, "ppc64bridge") == 0)
{
! ppc_cpu = PPC_OPCODE_PPC | PPC_OPCODE_64_BRIDGE | PPC_OPCODE_64;
ppc_size = PPC_OPCODE_64;
}
+ /* -mbooke32 means enable 32-bit BookE support. */
+ else if (strcmp (arg, "booke32") == 0)
+ ppc_cpu = PPC_OPCODE_PPC | PPC_OPCODE_BOOKE;
+ /* -mbooke means enable BookE support. */
+ else if (strcmp (arg, "booke") == 0)
+ {
+ ppc_cpu = PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_64;
+ ppc_size = PPC_OPCODE_64;
+ }
/* -mcom means assemble for the common intersection between Power
and PowerPC. At present, we just allow the union, rather
than the intersection. */
*************** PowerPC options:\n\
*** 1011,1020 ****
-mpwrx, -mpwr2 generate code for IBM POWER/2 (RIOS2)\n\
-mpwr generate code for IBM POWER (RIOS1)\n\
-m601 generate code for Motorola PowerPC 601\n\
! -mppc, -mppc32, -m403, -m405, -m603, -m604\n\
generate code for Motorola PowerPC 603/604\n\
-mppc64, -m620 generate code for Motorola PowerPC 620\n\
-mppc64bridge generate code for PowerPC 64, including bridge insns\n\
-mcom generate code Power/PowerPC common instructions\n\
-many generate code for any architecture (PWR/PWRX/PPC)\n\
-mregnames Allow symbolic names for registers\n\
--- 1027,1039 ----
-mpwrx, -mpwr2 generate code for IBM POWER/2 (RIOS2)\n\
-mpwr generate code for IBM POWER (RIOS1)\n\
-m601 generate code for Motorola PowerPC 601\n\
! -mppc, -mppc32, -m603, -m604\n\
generate code for Motorola PowerPC 603/604\n\
+ -m403, -m405 generate code for Motorola PowerPC 403/405\n\
-mppc64, -m620 generate code for Motorola PowerPC 620\n\
-mppc64bridge generate code for PowerPC 64, including bridge insns\n\
+ -mbooke generate code for Motorola BookE\n\
+ -mbooke32 generate code for 32-bit Motorola BookE\n\
-mcom generate code Power/PowerPC common instructions\n\
-many generate code for any architecture (PWR/PWRX/PPC)\n\
-mregnames Allow symbolic names for registers\n\
Index: gas/testsuite/gas/ppc/booke.d
===================================================================
RCS file: booke.d
diff -N booke.d
*** /dev/null Tue May 5 13:32:27 1998
--- booke.d Wed Oct 10 21:23:51 2001
***************
*** 0 ****
--- 1,130 ----
+ #as: -mbooke32
+ #objdump: -Dr -Mbooke32
+ #name: BookE tests
+
+ .*: +file format elf32-powerpc
+
+ Disassembly of section \.text:
+
+ 0+0000000 <start>:
+ 0: 24 25 00 30 bce 1,4\*cr1\+gt,30 <branch_target_1>
+ 4: 24 46 00 3d bcel 2,4\*cr1\+eq,40 <branch_target_2>
+ 8: 24 67 00 02 bcea 3,4\*cr1\+so,0 <start>
+ 8: R_PPC_ADDR14 branch_target_3
+ c: 24 88 00 03 bcela 4,4\*cr2,0 <start>
+ c: R_PPC_ADDR14 branch_target_4
+ 10: 4c a9 00 22 bclre 5,4\*cr2\+gt
+ 14: 4c aa 00 23 bclrel 5,4\*cr2\+eq
+ 18: 4d 0b 04 22 bcctre 8,4\*cr2\+so
+ 1c: 4d 0c 04 23 bcctrel 8,4\*cr3
+ 20: 58 00 00 74 be 94 <branch_target_5>
+ 24: 58 00 00 89 bel ac <branch_target_6>
+ 28: 58 00 00 02 bea 0 <start>
+ 28: R_PPC_ADDR24 branch_target_7
+ 2c: 58 00 00 03 bela 0 <start>
+ 2c: R_PPC_ADDR24 branch_target_8
+
+ 0+0000030 <branch_target_1>:
+ 30: e9 09 00 80 lbze r8,8\(r9\)
+ 34: e9 8f 00 41 lbzue r12,4\(r15\)
+ 38: 7c 86 40 fe lbzuxe r4,r6,r8
+ 3c: 7c 65 38 be lbzxe r3,r5,r7
+
+ 0+0000040 <branch_target_2>:
+ 40: f8 a6 06 40 lde r5,400\(r6\)
+ 44: f8 c7 07 11 ldue r6,452\(r7\)
+ 48: 7c e8 4e 3e ldxe r7,r8,r9
+ 4c: 7d 4b 66 7e ldxue r10,r11,r12
+
+ 0+0000050 <branch_target_3>:
+ 50: f9 81 02 06 lfde f12,128\(r1\)
+ 54: f8 25 00 47 lfdue f1,16\(r5\)
+ 58: 7c a1 1c be lfdxe f5,r1,r3
+ 5c: 7c c2 24 fe lfdxue f6,r2,r4
+ 60: f9 09 00 c4 lfse f8,48\(r9\)
+ 64: f9 2a 01 15 lfsue f9,68\(r10\)
+ 68: 7d 44 44 7e lfsuxe f10,r4,r8
+ 6c: 7d 23 3c 3e lfsxe f9,r3,r7
+
+ 0+0000070 <branch_target_4>:
+ 70: e9 45 03 24 lhae r10,50\(r5\)
+ 74: e8 23 00 55 lhaue r1,5\(r3\)
+ 78: 7c a1 1a fe lhauxe r5,r1,r3
+ 7c: 7f be fa be lhaxe r29,r30,r31
+ 80: 7c 22 1e 3c lhbrxe r1,r2,r3
+ 84: e8 83 01 22 lhze r4,18\(r3\)
+ 88: e8 c9 01 43 lhzue r6,20\(r9\)
+ 8c: 7c a7 4a 7e lhzuxe r5,r7,r9
+ 90: 7d 27 2a 3e lhzxe r9,r7,r5
+
+ 0+0000094 <branch_target_5>:
+ 94: 7d 4f a0 fc lwarxe r10,r15,r20
+ 98: 7c aa 94 3c lwbrxe r5,r10,r18
+ 9c: eb 9d 00 46 lwze r28,4\(r29\)
+ a0: e9 0a 02 87 lwzue r8,40\(r10\)
+ a4: 7c 66 48 7e lwzuxe r3,r6,r9
+ a8: 7f dd e0 3e lwzxe r30,r29,r28
+
+ 0+00000ac <branch_target_6>:
+ ac: 7c 06 3d fc dcbae r6,r7
+ b0: 7c 08 48 bc dcbfe r8,r9
+ b4: 7c 0a 5b bc dcbie r10,r11
+ b8: 7c 08 f0 7c dcbste r8,r30
+ bc: 7c c3 0a 3c dcbte 6,r3,r1
+ c0: 7c a4 11 fa dcbtste 5,r4,r2
+ c4: 7c 0f 77 fc dcbze r15,r14
+ c8: 7c 03 27 bc icbie r3,r4
+ cc: 7c a8 48 2c icbt 5,r8,r9
+ d0: 7c ca 78 3c icbte 6,r10,r15
+ d4: 7c a6 02 26 mfapidi r5,r6
+ d8: 7c 07 46 24 tlbivax r7,r8
+ dc: 7c 09 56 26 tlbivaxe r9,r10
+ e0: 7c 0b 67 24 tlbsx r11,r12
+ e4: 7c 0d 77 26 tlbsxe r13,r14
+
+ 0+00000e8 <branch_target_7>:
+ e8: 7c 22 1b 14 adde64 r1,r2,r3
+ ec: 7c 85 37 14 adde64o r4,r5,r6
+ f0: 7c e8 03 d4 addme64 r7,r8
+ f4: 7d 2a 07 d4 addme64o r9,r10
+ f8: 7d 6c 03 94 addze64 r11,r12
+ fc: 7d ae 07 94 addze64o r13,r14
+ 100: 7e 80 04 40 mcrxr64 cr5
+ 104: 7d f0 8b 10 subfe64 r15,r16,r17
+ 108: 7e 53 a7 10 subfe64o r18,r19,r20
+ 10c: 7e b6 03 d0 subfme64 r21,r22
+ 110: 7e f8 07 d0 subfme64o r23,r24
+ 114: 7f 3a 03 90 subfze64 r25,r26
+ 118: 7f 7c 07 90 subfze64o r27,r28
+
+ 0+000011c <branch_target_8>:
+ 11c: e8 22 03 28 stbe r1,50\(r2\)
+ 120: e8 64 02 89 stbue r3,40\(r4\)
+ 124: 7c a6 39 fe stbuxe r5,r6,r7
+ 128: 7d 09 51 be stbxe r8,r9,r10
+ 12c: 7d 6c 6b ff stdcxe\. r11,r12,r13
+ 130: f9 cf 00 78 stde r14,28\(r15\)
+ 134: fa 11 00 59 stdue r16,20\(r17\)
+ 138: 7e 53 a7 3e stdxe r18,r19,r20
+ 13c: 7e b6 bf 7e stdxue r21,r22,r23
+ 140: f8 38 00 3e stfde f1,12\(r24\)
+ 144: f8 59 00 0f stfdue f2,0\(r25\)
+ 148: 7c 7a dd be stfdxe f3,r26,r27
+ 14c: 7c 9c ed fe stfdxue f4,r28,r29
+ 150: 7c be ff be stfiwxe f5,r30,r31
+ 154: f8 de 00 6c stfse f6,24\(r30\)
+ 158: f8 fd 00 5d stfsue f7,20\(r29\)
+ 15c: 7d 1c dd 3e stfsxe f8,r28,r27
+ 160: 7d 3a cd 7e stfsxue f9,r26,r25
+ 164: 7f 17 b7 3c sthbrxe r24,r23,r22
+ 168: ea b4 01 ea sthe r21,30\(r20\)
+ 16c: ea 72 02 8b sthue r19,40\(r18\)
+ 170: 7e 30 7b 7e sthuxe r17,r16,r15
+ 174: 7d cd 63 3e sthxe r14,r13,r12
+ 178: 7d 6a 4d 3c stwbrxe r11,r10,r9
+ 17c: 7d 07 31 3d stwcxe\. r8,r7,r6
+ 180: e8 a4 03 2e stwe r5,50\(r4\)
+ 184: e8 62 02 8f stwue r3,40\(r2\)
+ 188: 7c 22 19 7e stwuxe r1,r2,r3
+ 18c: 7c 85 31 3e stwxe r4,r5,r6
+ Disassembly of section \.data:
Index: gas/testsuite/gas/ppc/booke.s
===================================================================
RCS file: booke.s
diff -N booke.s
*** /dev/null Tue May 5 13:32:27 1998
--- booke.s Wed Oct 10 21:23:51 2001
***************
*** 0 ****
--- 1,120 ----
+ # Motorola PowerPC BookE tests
+ #as: -mbooke32
+ .section ".text"
+ start:
+ bce 1, 5, branch_target_1
+ bcel 2, 6, branch_target_2
+ bcea 3, 7, branch_target_3
+ bcela 4, 8, branch_target_4
+ bclre 5, 9
+ bclrel 5, 10
+ bcctre 8, 11
+ bcctrel 8, 12
+ be branch_target_5
+ bel branch_target_6
+ bea branch_target_7
+ bela branch_target_8
+
+ branch_target_1:
+ lbze 8, 8(9)
+ lbzue 12, 4(15)
+ lbzuxe 4, 6, 8
+ lbzxe 3, 5, 7
+
+ branch_target_2:
+ lde 5, 400(6)
+ ldue 6, 452(7)
+ ldxe 7, 8, 9
+ ldxue 10, 11, 12
+
+ branch_target_3:
+ lfde 12, 128(1)
+ lfdue 1, 16(5)
+ lfdxe 5, 1, 3
+ lfdxue 6, 2, 4
+ lfse 8, 48(9)
+ lfsue 9, 68(10)
+ lfsuxe 10, 4, 8
+ lfsxe 9, 3, 7
+
+ branch_target_4:
+ lhae 10, 50(5)
+ lhaue 1, 5(3)
+ lhauxe 5, 1, 3
+ lhaxe 29, 30, 31
+ lhbrxe 1, 2, 3
+ lhze 4, 18(3)
+ lhzue 6, 20(9)
+ lhzuxe 5, 7, 9
+ lhzxe 9, 7, 5
+
+ branch_target_5:
+ lwarxe 10, 15, 20
+ lwbrxe 5, 10, 18
+ lwze 28, 4(29)
+ lwzue 8, 40(10)
+ lwzuxe 3, 6, 9
+ lwzxe 30, 29, 28
+
+ branch_target_6:
+ dcbae 6, 7
+ dcbfe 8, 9
+ dcbie 10, 11
+ dcbste 8, 30
+ dcbte 6, 3, 1
+ dcbtste 5, 4, 2
+ dcbze 15, 14
+ icbie 3, 4
+ icbt 5, 8, 9
+ icbte 6, 10, 15
+ mfapidi 5, 6
+ tlbivax 7, 8
+ tlbivaxe 9, 10
+ tlbsx 11, 12
+ tlbsxe 13, 14
+
+ branch_target_7:
+ adde64 1, 2, 3
+ adde64o 4, 5, 6
+ addme64 7, 8
+ addme64o 9, 10
+ addze64 11, 12
+ addze64o 13, 14
+ mcrxr64 5
+ subfe64 15, 16, 17
+ subfe64o 18, 19, 20
+ subfme64 21, 22
+ subfme64o 23, 24
+ subfze64 25, 26
+ subfze64o 27, 28
+
+ branch_target_8:
+ stbe 1, 50(2)
+ stbue 3, 40(4)
+ stbuxe 5, 6, 7
+ stbxe 8, 9, 10
+ stdcxe. 11, 12, 13
+ stde 14, 28(15)
+ stdue 16, 20(17)
+ stdxe 18, 19, 20
+ stdxue 21, 22, 23
+ stfde 1, 12(24)
+ stfdue 2, 0(25)
+ stfdxe 3, 26, 27
+ stfdxue 4, 28, 29
+ stfiwxe 5, 30, 31
+ stfse 6, 24(30)
+ stfsue 7, 20(29)
+ stfsxe 8, 28, 27
+ stfsxue 9, 26, 25
+ sthbrxe 24, 23, 22
+ sthe 21, 30(20)
+ sthue 19, 40(18)
+ sthuxe 17, 16, 15
+ sthxe 14, 13, 12
+ stwbrxe 11, 10, 9
+ stwcxe. 8, 7, 6
+ stwe 5, 50(4)
+ stwue 3, 40(2)
+ stwuxe 1, 2, 3
+ stwxe 4, 5, 6
Index: gas/testsuite/gas/ppc/ppc.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/ppc/ppc.exp,v
retrieving revision 1.2
diff -p -r1.2 ppc.exp
*** ppc.exp 2001/08/27 10:51:19 1.2
--- ppc.exp 2001/10/11 04:23:51
*************** if { [istarget powerpc64*-*-*] || [istar
*** 26,29 ****
--- 26,30 ----
if { [istarget powerpc*-*-*] } then {
run_dump_test "simpshft"
+ run_dump_test "booke"
}
Index: include/opcode/ppc.h
===================================================================
RCS file: /cvs/src/src/include/opcode/ppc.h,v
retrieving revision 1.7
diff -p -r1.7 ppc.h
*** ppc.h 2001/08/27 10:26:57 1.7
--- ppc.h 2001/10/11 04:23:55
*************** extern const int powerpc_num_opcodes;
*** 89,95 ****
#define PPC_OPCODE_64_BRIDGE (0400)
/* Opcode is supported by Altivec Vector Unit */
! #define PPC_OPCODE_ALTIVEC (01000)
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
--- 89,101 ----
#define PPC_OPCODE_64_BRIDGE (0400)
/* Opcode is supported by Altivec Vector Unit */
! #define PPC_OPCODE_ALTIVEC (01000)
!
! /* Opcode is supported by PowerPC 403 processor. */
! #define PPC_OPCODE_403 (02000)
!
! /* Opcode is supported by Motorola BookE processor. */
! #define PPC_OPCODE_BOOKE (04000)
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
Index: opcodes/ppc-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-dis.c,v
retrieving revision 1.4
diff -p -r1.4 ppc-dis.c
*** ppc-dis.c 2001/03/13 22:58:37 1.4
--- ppc-dis.c 2001/10/11 04:23:57
*************** Software Foundation, 59 Temple Place - S
*** 32,63 ****
static int print_insn_powerpc PARAMS ((bfd_vma, struct disassemble_info *,
int bigendian, int dialect));
! /* Print a big endian PowerPC instruction. For convenience, also
! disassemble instructions supported by the Motorola PowerPC 601
! and the Altivec vector unit. */
int
print_insn_big_powerpc (memaddr, info)
bfd_vma memaddr;
struct disassemble_info *info;
{
! return print_insn_powerpc (memaddr, info, 1,
! PPC_OPCODE_PPC | PPC_OPCODE_601 |
! PPC_OPCODE_ALTIVEC);
}
! /* Print a little endian PowerPC instruction. For convenience, also
! disassemble instructions supported by the Motorola PowerPC 601
! and the Altivec vector unit. */
int
print_insn_little_powerpc (memaddr, info)
bfd_vma memaddr;
struct disassemble_info *info;
{
! return print_insn_powerpc (memaddr, info, 0,
! PPC_OPCODE_PPC | PPC_OPCODE_601 |
! PPC_OPCODE_ALTIVEC);
}
/* Print a POWER (RS/6000) instruction. */
--- 32,76 ----
static int print_insn_powerpc PARAMS ((bfd_vma, struct disassemble_info *,
int bigendian, int dialect));
! static int powerpc_dialect PARAMS ((struct disassemble_info *));
+ /* Determine which set of machines to disassemble for. PPC403/601 or
+ Motorola BookE. For convenience, also disassemble instructions
+ supported by the AltiVec vector unit. */
+
+ int
+ powerpc_dialect(info)
+ struct disassemble_info *info;
+ {
+ int dialect = PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC;
+
+ if (info->disassembler_options &&
+ ((strcmp(info->disassembler_options, "booke") == 0) ||
+ (strcmp(info->disassembler_options, "booke32") == 0)))
+ dialect |= PPC_OPCODE_BOOKE;
+ else
+ dialect |= PPC_OPCODE_403 | PPC_OPCODE_601;
+ return dialect;
+ }
+
+ /* Print a big endian PowerPC instruction. */
+
int
print_insn_big_powerpc (memaddr, info)
bfd_vma memaddr;
struct disassemble_info *info;
{
! return print_insn_powerpc (memaddr, info, 1, powerpc_dialect(info));
}
! /* Print a little endian PowerPC instruction. */
int
print_insn_little_powerpc (memaddr, info)
bfd_vma memaddr;
struct disassemble_info *info;
{
! return print_insn_powerpc (memaddr, info, 0, powerpc_dialect(info));
}
/* Print a POWER (RS/6000) instruction. */
Index: opcodes/ppc-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-opc.c,v
retrieving revision 1.18
diff -p -r1.18 ppc-opc.c
*** ppc-opc.c 2001/09/14 10:52:26 1.18
--- ppc-opc.c 2001/10/11 04:23:59
*************** static unsigned long insert_boe PARAMS (
*** 55,60 ****
--- 55,64 ----
static long extract_boe PARAMS ((unsigned long, int *));
static unsigned long insert_ds PARAMS ((unsigned long, long, const char **));
static long extract_ds PARAMS ((unsigned long, int *));
+ static unsigned long insert_de PARAMS ((unsigned long, long, const char **));
+ static long extract_de PARAMS ((unsigned long, int *));
+ static unsigned long insert_des PARAMS ((unsigned long, long, const char **));
+ static long extract_des PARAMS ((unsigned long, int *));
static unsigned long insert_li PARAMS ((unsigned long, long, const char **));
static long extract_li PARAMS ((unsigned long, int *));
static unsigned long insert_mbe PARAMS ((unsigned long, long, const char **));
*************** const struct powerpc_operand powerpc_ope
*** 189,203 ****
#define CR BT + 1
{ 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
/* The D field in a D form instruction. This is a displacement off
a register, and implies that the next operand is a register in
parentheses. */
! #define D CR + 1
{ 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
/* The DS field in a DS form instruction. This is like D, but the
lower two bits are forced to zero. */
! #define DS D + 1
{ 16, 0, insert_ds, extract_ds,
PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
--- 193,221 ----
#define CR BT + 1
{ 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
+ /* The CT field in an X form instruction. */
+ #define CT CR + 1
+ { 5, 21, 0, 0, 0 },
+
/* The D field in a D form instruction. This is a displacement off
a register, and implies that the next operand is a register in
parentheses. */
! #define D CT + 1
{ 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
+ /* The DE field in a DE form instruction. This is like D, but is 12
+ bits only. */
+ #define DE D + 1
+ { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
+
+ /* The DES field in a DES form instruction. This is like DS, but is 14
+ bits only (12 stored.) */
+ #define DES DE + 1
+ { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
+
/* The DS field in a DS form instruction. This is like D, but the
lower two bits are forced to zero. */
! #define DS DES + 1
{ 16, 0, insert_ds, extract_ds,
PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
*************** extract_ds (insn, invalid)
*** 701,706 ****
--- 719,775 ----
return insn & 0xfffc;
}
+ /* The DE field in a DE form instruction. */
+
+ /*ARGSUSED*/
+ static unsigned long
+ insert_de (insn, value, errmsg)
+ unsigned long insn;
+ long value;
+ const char **errmsg ATTRIBUTE_UNUSED;
+ {
+ if ((value > 2047 || value < -2048) && errmsg != NULL)
+ *errmsg = _("offset not between -2048 and 2047");
+ return insn | ((value << 4) & 0xfff0);
+ }
+
+ /*ARGSUSED*/
+ static long
+ extract_de (insn, invalid)
+ unsigned long insn;
+ int *invalid ATTRIBUTE_UNUSED;
+ {
+ return (insn & 0xfff0) >> 4;
+ }
+
+ /* The DES field in a DES form instruction. */
+
+ /*ARGSUSED*/
+ static unsigned long
+ insert_des (insn, value, errmsg)
+ unsigned long insn;
+ long value;
+ const char **errmsg;
+ {
+ if ((value > 8191 || value < -8192) && errmsg != NULL)
+ *errmsg = _("offset not between -8192 and 8191");
+ else if ((value & 3) != 0 && errmsg != NULL)
+ *errmsg = _("offset not a multiple of 4");
+ return insn | ((value << 2) & 0xfff0);
+ }
+
+ /*ARGSUSED*/
+ static long
+ extract_des (insn, invalid)
+ unsigned long insn;
+ int *invalid ATTRIBUTE_UNUSED;
+ {
+ if ((insn & 0x8000) != 0)
+ return ((insn & 0xfff0) >> 2) - 0x4000;
+ else
+ return (insn & 0xfff0) >> 2;
+ }
+
/* The LI field in an I form instruction. The lower two bits are
forced to zero. */
*************** extract_tbr (insn, invalid)
*** 1112,1117 ****
--- 1181,1190 ----
#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
#define DS_MASK DSO (0x3f, 3)
+ /* A DE form instruction. */
+ #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
+ #define DE_MASK DEO (0x3e, 0xf)
+
/* An M form instruction. */
#define M(op, rc) (OP (op) | ((rc) & 1))
#define M_MASK M (0x3f, 1)
*************** extract_tbr (insn, invalid)
*** 1336,1344 ****
#define PPC PPC_OPCODE_PPC | PPC_OPCODE_ANY
#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
#define PPC32 PPC_OPCODE_PPC | PPC_OPCODE_32 | PPC_OPCODE_ANY
! #define PPC64 PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_ANY
#define PPCONLY PPC_OPCODE_PPC
! #define PPC403 PPC
#define PPC405 PPC403
#define PPC750 PPC
#define PPC860 PPC
--- 1409,1417 ----
#define PPC PPC_OPCODE_PPC | PPC_OPCODE_ANY
#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
#define PPC32 PPC_OPCODE_PPC | PPC_OPCODE_32 | PPC_OPCODE_ANY
! #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_ANY
#define PPCONLY PPC_OPCODE_PPC
! #define PPC403 PPC_OPCODE_403
#define PPC405 PPC403
#define PPC750 PPC
#define PPC860 PPC
*************** extract_tbr (insn, invalid)
*** 1353,1358 ****
--- 1426,1432 ----
#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
#define MFDEC1 PPC_OPCODE_POWER
#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601
+ #define BOOKE PPC_OPCODE_BOOKE
/* The opcode table.
*************** const struct powerpc_opcode powerpc_opco
*** 1670,1675 ****
--- 1744,1754 ----
{ "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
+ { "bce", B(9,0,0), B_MASK, BOOKE, { BO, BI, BD } },
+ { "bcel", B(9,0,1), B_MASK, BOOKE, { BO, BI, BD } },
+ { "bcea", B(9,1,0), B_MASK, BOOKE, { BO, BI, BDA } },
+ { "bcela", B(9,1,1), B_MASK, BOOKE, { BO, BI, BDA } },
+
{ "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
{ "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
{ "cmpli", OP(10), OP_MASK, PPCONLY, { BF, L, RA, UI } },
*************** const struct powerpc_opcode powerpc_opco
*** 2136,2141 ****
--- 2215,2223 ----
{ "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
{ "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
+ { "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE, { BO, BI } },
+ { "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE, { BO, BI } },
+
{ "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } },
{ "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
*************** const struct powerpc_opcode powerpc_opco
*** 2260,2265 ****
--- 2342,2349 ----
{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
{ "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
{ "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
+ { "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE, { BO, BI } },
+ { "bcctrel", XLLK(19,529,1), XLYBB_MASK, BOOKE, { BO, BI } },
{ "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
{ "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
*************** const struct powerpc_opcode powerpc_opco
*** 2279,2284 ****
--- 2363,2373 ----
{ "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
{ "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
+ { "be", B(22,0,0), B_MASK, BOOKE, { LI } },
+ { "bel", B(22,0,1), B_MASK, BOOKE, { LI } },
+ { "bea", B(22,1,0), B_MASK, BOOKE, { LIA } },
+ { "bela", B(22,1,1), B_MASK, BOOKE, { LIA } },
+
{ "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
{ "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
{ "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
*************** const struct powerpc_opcode powerpc_opco
*** 2400,2405 ****
--- 2489,2496 ----
{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA, RB } },
+ { "icbt", X(31,22), X_MASK, BOOKE, { CT, RA, RB } },
+
{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA, RB } },
{ "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
*************** const struct powerpc_opcode powerpc_opco
*** 2422,2427 ****
--- 2513,2522 ----
{ "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
{ "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
+ { "icbte", X(31,30), X_MASK, BOOKE, { CT, RA, RB } },
+
+ { "lwzxe", X(31,31), X_MASK, BOOKE, { RT, RA, RB } },
+
{ "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
{ "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
{ "cmpl", X(31,32), XCMP_MASK, PPCONLY, { BF, L, RA, RB } },
*************** const struct powerpc_opcode powerpc_opco
*** 2443,2448 ****
--- 2538,2547 ----
{ "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
{ "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
+ { "dcbste", X(31,62), XRT_MASK, BOOKE, { RA, RB } },
+
+ { "lwzuxe", X(31,63), X_MASK, BOOKE, { RT, RAL, RB } },
+
{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
*************** const struct powerpc_opcode powerpc_opco
*** 2481,2486 ****
--- 2580,2589 ----
{ "lbzx", X(31,87), X_MASK, COM, { RT, RA, RB } },
+ { "dcbfe", X(31,94), XRT_MASK, BOOKE, { RA, RB } },
+
+ { "lbzxe", X(31,95), X_MASK, BOOKE, { RT, RA, RB } },
+
{ "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
{ "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
{ "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
*************** const struct powerpc_opcode powerpc_opco
*** 2502,2507 ****
--- 2605,2614 ----
{ "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
{ "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
+ { "lwarxe", X(31,126), X_MASK, BOOKE, { RT, RA, RB } },
+
+ { "lbzuxe", X(31,127), X_MASK, BOOKE, { RT, RAL, RB } },
+
{ "wrtee", X(31,131), XRARB_MASK, PPC403, { RS } },
{ "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
*************** const struct powerpc_opcode powerpc_opco
*** 2534,2539 ****
--- 2641,2650 ----
{ "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA, RB } },
{ "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
+ { "stwcxe.", XRC(31,158,1), X_MASK, BOOKE, { RS, RA, RB } },
+
+ { "stwxe", X(31,159), X_MASK, BOOKE, { RS, RA, RB } },
+
{ "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
{ "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
*************** const struct powerpc_opcode powerpc_opco
*** 2552,2557 ****
--- 2663,2670 ----
{ "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
{ "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
+ { "stwuxe", X(31,191), X_MASK, BOOKE, { RS, RAS, RB } },
+
{ "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
{ "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
{ "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
*************** const struct powerpc_opcode powerpc_opco
*** 2582,2587 ****
--- 2695,2702 ----
{ "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
{ "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
+ { "stbxe", X(31,223), X_MASK, BOOKE, { RS, RA, RB } },
+
{ "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
{ "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
{ "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
*************** const struct powerpc_opcode powerpc_opco
*** 2617,2629 ****
{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
{ "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
! { "dcbtst", X(31,246), XRT_MASK, PPC, { RA, RB } },
{ "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
{ "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
{ "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
{ "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
--- 2732,2748 ----
{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
{ "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
! { "dcbtst", X(31,246), XRT_MASK, PPC, { CT, RA, RB } },
{ "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
{ "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
{ "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
+ { "dcbtste", X(31,253), X_MASK, BOOKE, { CT, RA, RB } },
+
+ { "stbuxe", X(31,255), X_MASK, BOOKE, { RS, RAS, RB } },
+
{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
{ "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
*************** const struct powerpc_opcode powerpc_opco
*** 2640,2655 ****
{ "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
{ "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
{ "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
{ "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
! { "dcbt", X(31,278), XRT_MASK, PPC, { RA, RB } },
{ "lhzx", X(31,279), X_MASK, COM, { RT, RA, RB } },
{ "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
{ "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
{ "tlbie", X(31,306), XRTRA_MASK, PPC, { RB } },
{ "tlbi", X(31,306), XRT_MASK, POWER, { RA, RB } },
--- 2759,2780 ----
{ "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
{ "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
+ { "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
+
{ "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
{ "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
! { "dcbt", X(31,278), XRT_MASK, PPC, { CT, RA, RB } },
{ "lhzx", X(31,279), X_MASK, COM, { RT, RA, RB } },
{ "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
{ "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
+ { "dcbte", X(31,286), X_MASK, BOOKE, { CT, RA, RB } },
+
+ { "lhzxe", X(31,287), X_MASK, BOOKE, { RT, RA, RB } },
+
{ "tlbie", X(31,306), XRTRA_MASK, PPC, { RB } },
{ "tlbi", X(31,306), XRT_MASK, POWER, { RA, RB } },
*************** const struct powerpc_opcode powerpc_opco
*** 2660,2665 ****
--- 2785,2792 ----
{ "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
{ "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
+ { "lhzuxe", X(31,319), X_MASK, BOOKE, { RT, RAL, RB } },
+
{ "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
{ "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
{ "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
*************** const struct powerpc_opcode powerpc_opco
*** 2837,2842 ****
--- 2964,2971 ----
{ "lhax", X(31,343), X_MASK, COM, { RT, RA, RB } },
+ { "lhaxe", X(31,351), X_MASK, BOOKE, { RT, RA, RB } },
+
{ "dccci", X(31,454), XRT_MASK, PPC403, { RA, RB } },
{ "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
*************** const struct powerpc_opcode powerpc_opco
*** 2859,2864 ****
--- 2988,3001 ----
{ "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
+ { "lhauxe", X(31,383), X_MASK, BOOKE, { RT, RAL, RB } },
+
+ { "subfe64", XO(31,392,0,0), XO_MASK, BOOKE, { RT, RA, RB } },
+ { "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE, { RT, RA, RB } },
+
+ { "adde64", XO(31,394,0,0), XO_MASK, BOOKE, { RT, RA, RB } },
+ { "adde64o", XO(31,394,1,0), XO_MASK, BOOKE, { RT, RA, RB } },
+
{ "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
{ "sthx", X(31,407), X_MASK, COM, { RS, RA, RB } },
*************** const struct powerpc_opcode powerpc_opco
*** 2877,2888 ****
--- 3014,3029 ----
{ "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
{ "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
+ { "sthxe", X(31,415), X_MASK, BOOKE, { RS, RA, RB } },
+
{ "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
{ "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
+ { "sthuxe", X(31,447), X_MASK, BOOKE, { RS, RAS, RB } },
+
{ "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
{ "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
{ "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
*************** const struct powerpc_opcode powerpc_opco
*** 2924,2934 ****
--- 3065,3081 ----
{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RT } },
{ "mtdcr", X(31,451), X_MASK, PPC403, { SPR, RS } },
+ { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE, { RT, RA } },
+ { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE, { RT, RA } },
+
{ "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
{ "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
{ "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
{ "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
+ { "addze64", XO(31,458,0,0), XORB_MASK, BOOKE, { RT, RA } },
+ { "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE, { RT, RA } },
+
{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
*************** const struct powerpc_opcode powerpc_opco
*** 3043,3053 ****
--- 3190,3204 ----
{ "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
{ "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
+ { "dcbie", X(31,478), XRT_MASK, BOOKE, { RA, RB } },
+
{ "dcread", X(31,486), X_MASK, PPC403, { RT, RA, RB }},
{ "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
+ { "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE, { RT, RA } },
{ "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
{ "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
+ { "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE, { RT, RA } },
{ "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
{ "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
*************** const struct powerpc_opcode powerpc_opco
*** 3055,3060 ****
--- 3206,3214 ----
{ "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
{ "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
+ { "addme64", XO(31,490,0,0), XORB_MASK, BOOKE, { RT, RA } },
+ { "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE, { RT, RA } },
+
{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
*************** const struct powerpc_opcode powerpc_opco
*** 3064,3071 ****
--- 3218,3229 ----
{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
+ { "stdcxe.", XRC(31,511,1), X_MASK, BOOKE, { RS, RA, RB } },
+
{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
+ { "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE, { BF } },
+
{ "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
{ "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA, RB } },
*************** const struct powerpc_opcode powerpc_opco
*** 3090,3099 ****
--- 3248,3263 ----
{ "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
{ "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
+ { "lwbrxe", X(31,542), X_MASK, BOOKE, { RT, RA, RB } },
+
+ { "lfsxe", X(31,543), X_MASK, BOOKE, { FRT, RA, RB } },
+
{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
{ "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
+ { "lfsuxe", X(31,575), X_MASK, BOOKE, { FRT, RAS, RB } },
+
{ "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA, NB } },
*************** const struct powerpc_opcode powerpc_opco
*** 3106,3117 ****
--- 3270,3285 ----
{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA, RB } },
+ { "lfdxe", X(31,607), X_MASK, BOOKE, { FRT, RA, RB } },
+
{ "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
{ "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
{ "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
+ { "lfdxue", X(31,639), X_MASK, BOOKE, { FRT, RAS, RB } },
+
{ "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
{ "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA, RB } },
*************** const struct powerpc_opcode powerpc_opco
*** 3128,3138 ****
--- 3296,3312 ----
{ "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
{ "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
+ { "stwbrxe", X(31,670), X_MASK, BOOKE, { RS, RA, RB } },
+
+ { "stfsxe", X(31,671), X_MASK, BOOKE, { FRS, RA, RB } },
+
{ "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
{ "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
{ "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
+ { "stfsxue", X(31,703), X_MASK, BOOKE, { FRS, RAS, RB } },
+
{ "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA, NB } },
{ "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA, NB } },
*************** const struct powerpc_opcode powerpc_opco
*** 3144,3149 ****
--- 3318,3325 ----
{ "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
{ "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
+ { "stfdxe", X(31,735), X_MASK, BOOKE, { FRS, RA, RB } },
+
{ "dcba", X(31,758), XRT_MASK, PPC405, { RA, RB } },
{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
*************** const struct powerpc_opcode powerpc_opco
*** 3151,3156 ****
--- 3327,3339 ----
{ "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
{ "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
+ { "dcbae", X(31,766), XRT_MASK, BOOKE, { RA, RB } },
+
+ { "stfdxue", X(31,767), X_MASK, BOOKE, { FRS, RAS, RB } },
+
+ { "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
+ { "tlbivaxe",X(31,787), XRT_MASK, BOOKE, { RA, RB } },
+
{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA, RB } },
{ "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
*************** const struct powerpc_opcode powerpc_opco
*** 3161,3166 ****
--- 3344,3354 ----
{ "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
{ "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
+ { "lhbrxe", X(31,798), X_MASK, BOOKE, { RT, RA, RB } },
+
+ { "ldxe", X(31,799), X_MASK, BOOKE, { RT, RA, RB } },
+ { "ldxue", X(31,831), X_MASK, BOOKE, { RT, RA, RB } },
+
{ "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
{ "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
*************** const struct powerpc_opcode powerpc_opco
*** 3175,3180 ****
--- 3363,3371 ----
{ "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } },
{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } },
+ { "tlbsx", XRC(31,914,0), X_MASK, BOOKE, { RA, RB } },
+ { "tlbsxe", XRC(31,915,0), X_MASK, BOOKE, { RA, RB } },
+
{ "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA, RB } },
*************** const struct powerpc_opcode powerpc_opco
*** 3190,3198 ****
{ "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
{ "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
- { "tlbre", X(31,946), X_MASK, PPC403, { RT, RA, SH } },
{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
{ "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
--- 3381,3394 ----
{ "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
{ "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
+ { "sthbrxe", X(31,926), X_MASK, BOOKE, { RS, RA, RB } },
+
+ { "stdxe", X(31,927), X_MASK, BOOKE, { RS, RA, RB } },
+
+ { "tlbre", X(31,946), X_MASK, BOOKE, { RT, RA, SH } },
+
{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
{ "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
*************** const struct powerpc_opcode powerpc_opco
*** 3200,3205 ****
--- 3396,3403 ----
{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
+ { "stdxue", X(31,959), X_MASK, BOOKE, { RS, RAS, RB } },
+
{ "iccci", X(31,966), XRT_MASK, PPC403, { RA, RB } },
{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
*************** const struct powerpc_opcode powerpc_opco
*** 3217,3227 ****
--- 3415,3430 ----
{ "icread", X(31,998), XRT_MASK, PPC403, { RA, RB } },
+ { "icbie", X(31,990), XRT_MASK, BOOKE, { RA, RB } },
+ { "stfiwxe", X(31,991), X_MASK, BOOKE, { FRS, RA, RB } },
+
{ "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
+ { "dcbze", X(31,1022), XRT_MASK, BOOKE, { RA, RB } },
+
{ "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
{ "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
{ "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
*************** const struct powerpc_opcode powerpc_opco
*** 3299,3304 ****
--- 3502,3522 ----
{ "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA } },
+ { "lbze", DEO(58,0), DE_MASK, BOOKE, { RT, DE, RA } },
+ { "lbzue", DEO(58,1), DE_MASK, BOOKE, { RT, DE, RAL } },
+ { "lhze", DEO(58,2), DE_MASK, BOOKE, { RT, DE, RA } },
+ { "lhzue", DEO(58,3), DE_MASK, BOOKE, { RT, DE, RAL } },
+ { "lhae", DEO(58,4), DE_MASK, BOOKE, { RT, DE, RA } },
+ { "lhaue", DEO(58,5), DE_MASK, BOOKE, { RT, DE, RAL } },
+ { "lwze", DEO(58,6), DE_MASK, BOOKE, { RT, DE, RA } },
+ { "lwzue", DEO(58,7), DE_MASK, BOOKE, { RT, DE, RAL } },
+ { "stbe", DEO(58,8), DE_MASK, BOOKE, { RS, DE, RA } },
+ { "stbue", DEO(58,9), DE_MASK, BOOKE, { RS, DE, RAS } },
+ { "sthe", DEO(58,10), DE_MASK, BOOKE, { RS, DE, RA } },
+ { "sthue", DEO(58,11), DE_MASK, BOOKE, { RS, DE, RAS } },
+ { "stwe", DEO(58,14), DE_MASK, BOOKE, { RS, DE, RA } },
+ { "stwue", DEO(58,15), DE_MASK, BOOKE, { RS, DE, RAS } },
+
{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
*************** const struct powerpc_opcode powerpc_opco
*** 3333,3341 ****
--- 3551,3574 ----
{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
+ { "lde", DEO(62,0), DE_MASK, BOOKE, { RT, DES, RA } },
+
{ "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA } },
+ { "ldue", DEO(62,1), DE_MASK, BOOKE, { RT, DES, RA } },
+
{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
+
+ { "lfse", DEO(62,4), DE_MASK, BOOKE, { FRT, DES, RA } },
+ { "lfsue", DEO(62,5), DE_MASK, BOOKE, { FRT, DES, RAS } },
+ { "lfde", DEO(62,6), DE_MASK, BOOKE, { FRT, DES, RA } },
+ { "lfdue", DEO(62,7), DE_MASK, BOOKE, { FRT, DES, RAS } },
+ { "stde", DEO(62,8), DE_MASK, BOOKE, { RS, DES, RA } },
+ { "stdue", DEO(62,9), DE_MASK, BOOKE, { RS, DES, RAS } },
+ { "stfse", DEO(62,12), DE_MASK, BOOKE, { FRS, DES, RA } },
+ { "stfsue", DEO(62,13), DE_MASK, BOOKE, { FRS, DES, RAS } },
+ { "stfde", DEO(62,14), DE_MASK, BOOKE, { FRS, DES, RA } },
+ { "stfdue", DEO(62,15), DE_MASK, BOOKE, { FRS, DES, RAS } },
{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
More information about the Binutils
mailing list