[patch] Some improvements for m68k/ColdFire
Peter Jakubek
pjak@snafu.de
Sun May 27 07:31:00 GMT 2001
Patches to correct some 68k/ColdFire problems:
-----------------------------------------------------------------------------
src/gas ChangeLog:
2001-05-27 Peter Jakubek <pjak@snafu.de>
* gas/config/tc-m68k.c (md_show_usage): Add all supported ColdFire
options to list (e.g. m5206e, m5307, m5407).
diff -ru src.orig/gas/config/tc-m68k.c src/gas/config/tc-m68k.c
--- src.orig/gas/config/tc-m68k.c Sun May 27 12:04:44 2001
+++ src/gas/config/tc-m68k.c Sun May 27 12:05:37 2001
@@ -6888,8 +6888,8 @@
680X0 options:\n\
-l use 1 word for refs to undefined symbols [default 2]\n\
-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
- | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
- | -mcpu32 | -m5200\n\
+ | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32\n\
+ | -m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m5307 | -m5407\n\
specify variant of 680X0 architecture [default 68020]\n\
-m68881 | -m68882 | -mno-68881 | -mno-68882\n\
target has/lacks floating-point coprocessor\n\
-----------------------------------------------------------------------------
src/opcodes ChangeLog:
2001-05-27 Peter Jakubek <pjak@snafu.de>
* opcodes/m68k-dis.c (print_insn_m68k): Fix typo.
* opcodes/m68k-opc.c (m68k_opcodes): Correct allowed operands for
mcf (ColdFire) div, rem and moveb instructions.
diff -ru src.orig/opcodes/m68k-dis.c src/opcodes/m68k-dis.c
--- src.orig/opcodes/m68k-dis.c Sun May 27 12:04:44 2001
+++ src/opcodes/m68k-dis.c Sun May 27 12:05:37 2001
@@ -268,7 +268,7 @@
arch_mask = mcf5206e;
break;
case bfd_mach_mcf5307:
- arch_mask = mcf5407;
+ arch_mask = mcf5307;
break;
case bfd_mach_mcf5407:
arch_mask = mcf5407;
diff -ru src.orig/opcodes/m68k-opc.c src/opcodes/m68k-opc.c
--- src.orig/opcodes/m68k-opc.c Sun May 27 12:04:44 2001
+++ src/opcodes/m68k-opc.c Sun May 27 12:05:37 2001
@@ -305,22 +305,20 @@
{"dbvc", one(0054310), one(0177770), "DsBw", m68000up },
{"dbvs", one(0054710), one(0177770), "DsBw", m68000up },
-{"divsw", one(0100700), one(0170700), ";wDd", m68000up },
-{"divsw", one(0100700), one(0170700), "vsDd", mcf5307up | mcf5206e },
+{"divsw", one(0100700), one(0170700), ";wDd", m68000up | mcf5307up | mcf5206e },
{"divsl", two(0046100,0006000),two(0177700,0107770),";lD3D1", m68020up|cpu32 },
{"divsl", two(0046100,0004000),two(0177700,0107770),";lDD", m68020up|cpu32 },
-{"divsl", two(0046100,0004000),two(0177700,0107770),"vsDD", mcf5307up | mcf5206e },
+{"divsl", two(0046100,0004000),two(0177700,0107770),"qsDD", mcf5307up | mcf5206e },
{"divsll", two(0046100,0004000),two(0177700,0107770),";lD3D1",m68020up|cpu32 },
{"divsll", two(0046100,0004000),two(0177700,0107770),";lDD", m68020up|cpu32 },
-{"divuw", one(0100300), one(0170700), ";wDd", m68000up },
-{"divuw", one(0100300), one(0170700), "vsDd", mcf5307up | mcf5206e },
+{"divuw", one(0100300), one(0170700), ";wDd", m68000up | mcf5307up | mcf5206e },
{"divul", two(0046100,0002000),two(0177700,0107770),";lD3D1", m68020up|cpu32 },
{"divul", two(0046100,0000000),two(0177700,0107770),";lDD", m68020up|cpu32 },
-{"divul", two(0046100,0000000),two(0177700,0107770),"vsDD", mcf5307up | mcf5206e },
+{"divul", two(0046100,0000000),two(0177700,0107770),"qsDD", mcf5307up | mcf5206e },
{"divull", two(0046100,0000000),two(0177700,0107770),";lD3D1",m68020up|cpu32 },
{"divull", two(0046100,0000000),two(0177700,0107770),";lDD", m68020up|cpu32 },
@@ -1340,9 +1338,15 @@
/* The move opcode can generate the movea and moveq instructions. */
{"moveb", one(0010000), one(0170000), ";b$d", m68000up },
-{"moveb", one(0010000), one(0170000), "ms%d", mcf },
-{"moveb", one(0010000), one(0170000), "nspd", mcf },
-{"moveb", one(0010000), one(0170000), "obmd", mcf },
+{"moveb", one(0010000), one(0170070), "Ds$d", mcf },
+{"moveb", one(0010020), one(0170070), "as$d", mcf },
+{"moveb", one(0010030), one(0170070), "+s$d", mcf },
+{"moveb", one(0010040), one(0170070), "-s$d", mcf },
+{"moveb", one(0010000), one(0170000), "nsqd", mcf },
+{"moveb", one(0010000), one(0170700), "obDd", mcf },
+{"moveb", one(0010200), one(0170700), "obad", mcf },
+{"moveb", one(0010300), one(0170700), "ob+d", mcf },
+{"moveb", one(0010400), one(0170700), "ob-d", mcf },
{"moveb", one(0010000), one(0170000), "obnd", mcf5407 },
{"movew", one(0030000), one(0170000), "*w%d", m68000up },
@@ -1732,8 +1736,8 @@
{"pvalid", two(0xf000, 0x2c00), two(0xffc0, 0xfff8), "A3&s", m68851 },
/* FIXME: don't allow Dw==Dx. */
-{"remsl", two(0x4c40, 0x0800), two(0xffc0, 0x8ff8), "vsD3D1", mcf5307up | mcf5206e },
-{"remul", two(0x4c40, 0x0000), two(0xffc0, 0x8ff8), "vsD3D1", mcf5307up | mcf5206e },
+{"remsl", two(0x4c40, 0x0800), two(0xffc0, 0x8ff8), "qsD3D1", mcf5307up | mcf5206e },
+{"remul", two(0x4c40, 0x0000), two(0xffc0, 0x8ff8), "qsD3D1", mcf5307up | mcf5206e },
{"reset", one(0047160), one(0177777), "", m68000up },
--
Peter Jakubek
pjak@snafu.de
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