RFC: PowerPC GAS changes

Geoff Keating geoffk@cygnus.com
Wed Sep 6 16:28:00 GMT 2000


> Date: Wed, 06 Sep 2000 16:02:30 -0700
> From: Mark Hatle <fray@mvista.com>

> > There is support for doing this kind of thing already.  For instance,
> > try using the POWER instruction 'mfmq' with -mppc:
> > 
> > [geoffk@envy geoffk]$ cat > t.s
> >         mfmq %r3
> > [geoffk@envy geoffk]$ as -m601 t.s -o t.o
> > [geoffk@envy geoffk]$ as -mpwr t.s -o t.o
> > [geoffk@envy geoffk]$ as -mppc t.s -o t.o
> > t.s: Assembler messages:
> > t.s:1: Error: Unrecognized opcode: `mfmq'
> > 
> > it's just a question of getting the flag arrangement right.
> 
> That is correct, however if you specify -m603, -m604, -m750, -m403,
> -m405, -m860 you get exactly the same assembly info.  The biggest
> problem is we only have 32 bits of space in "flags".  I can fill all 32
> bits quickly with what is already there and add in CPU types of 603,
> 604, 620, 750, 7400, 8xx, 4xx, 403, 405, etc..  (you get the point)

We presently have only 10 bits of 'flags' used.  That leaves 22 bits
free.

For instructions that only work on one CPU, you could allocate say 6
bits and make them a CPU number and require that the CPU number must
match the specified CPU or be zero.  For shared instructions (like
dcba or fres), use a flag bit.  There aren't that many categories of
shared instruction.  If two processors just coincidentally share an
instruction, you could just duplicate the entry in the opcode table.

-- 
- Geoffrey Keating <geoffk@cygnus.com>


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