[patch] add SiByte SB-1 name recognition to MIPS bits

Chris G. Demetriou cgd@sibyte.com
Wed Oct 18 14:19:00 GMT 2000


The patch below adds recognition of reasonable SB-1 cpu & target names
to the MIPS bits.  There's also one little unrelated documentation fix
that I noticed along the way, in gas/doc/as.texinfo.

(Eventually we'll also be submitting back changes to the instruction
table for some additional MIPS32 stuff, for MIPS64, and for the SB-1
extensions, but now is not yet the time.  These changes help us merge
our source tree, so it'll be easier to submit those changes when we
can.)

patch applies in src, on top of all of the previous patches I've
sent.  ChangeLog entries split out by directory as usual.

tested on mips-elf, mips64-elf, mips-linux (with all of my previous
changes also applied), no new failures.


chris
=============================================================================
for bfd/ChangeLog:

	* bfd/aoutx.h (NAME(aout,machine_type)): Add a
	bfd_mach_mips_sb1 case.
	* bfd/archures.c (bfd_mach_mips_sb1): New constant.
	* bfd/bfd-in2.h (bfd_mach_mips_sb1): New constant.
	* bfd/cpu-mips.c (I_sb1): New constant.
	(arch_info_struct): Add entry for bfd_mach_mips_sb1.
	* bfd/elf32-mips.c (elf_mips_mach): Add case for
	E_MIPS_MACH_SB1.
	(_bfd_mips_elf_final_write_processing): Add case for
	bfd_mach_mips_sb1.


for binutils/ChangeLog:

	* readelf.c (get_machine_flags): Add case for
	E_MIPS_MACH_SB1.


for gas/ChangeLog:

	* config/tc-mips.c (md_show_usage): Add "sb1" to the
	CPU list.
	(mips_cpu_info_table): Add SB-1 entries.
	* doc/c-mips.texi: Add "sb1" to the list of CPUs
	known to the -mcpu option.
	
	* doc/as.texinfo: Correct description of MIPS -mcpu
	option, by copying some of the text from doc/c-mips.texi.


for include/elf/ChangeLog:

	* mips.h (E_MIPS_MACH_SB1): New constant.


for include/opcode/ChangeLog:

	* mips.h (CPU_SB1): New constant.


For opcodes/ChangeLog:

	* mips-dis.c (set_mips_isa_type): Add case for
	bfd_mach_mips_sb1.


diff -rcp ../src.P08/bfd/aoutx.h ./bfd/aoutx.h
*** ../src.P08/bfd/aoutx.h	Mon Oct 16 16:27:11 2000
--- ./bfd/aoutx.h	Wed Oct 18 12:45:23 2000
*************** NAME(aout,machine_type) (arch, machine, 
*** 782,787 ****
--- 782,788 ----
      case bfd_mach_mips32_4k:
      case bfd_mach_mips5:
      case bfd_mach_mips64:
+     case bfd_mach_mips_sb1:
        /* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc.  */
        arch_flags = M_MIPS2;
        break;
diff -rcp ../src.P08/bfd/archures.c ./bfd/archures.c
*** ../src.P08/bfd/archures.c	Mon Oct 16 16:27:32 2000
--- ./bfd/archures.c	Wed Oct 18 12:45:51 2000
*************** DESCRIPTION
*** 132,137 ****
--- 132,138 ----
  .#define bfd_mach_mips32_4k		3204113	{* 32, 04, octal 'K' *}
  .#define bfd_mach_mips5			5
  .#define bfd_mach_mips64		64
+ .#define bfd_mach_mips_sb1		12310201 {* octal 'SB', 01 *}
  .  bfd_arch_i386,      {* Intel 386 *}
  .#define bfd_mach_i386_i386 0
  .#define bfd_mach_i386_i8086 1
diff -rcp ../src.P08/bfd/bfd-in2.h ./bfd/bfd-in2.h
*** ../src.P08/bfd/bfd-in2.h	Mon Oct 16 16:27:59 2000
--- ./bfd/bfd-in2.h	Wed Oct 18 12:46:06 2000
*************** enum bfd_architecture 
*** 1402,1407 ****
--- 1402,1408 ----
  #define bfd_mach_mips32_4k	       3204113	/* 32, 04, octal 'K' */
  #define bfd_mach_mips5		       5
  #define bfd_mach_mips64		       64
+ #define bfd_mach_mips_sb1	       12310201	/* octal 'SB', 01 */
    bfd_arch_i386,      /* Intel 386 */
  #define bfd_mach_i386_i386 0
  #define bfd_mach_i386_i8086 1
diff -rcp ../src.P08/bfd/cpu-mips.c ./bfd/cpu-mips.c
*** ../src.P08/bfd/cpu-mips.c	Mon Oct 16 16:29:10 2000
--- ./bfd/cpu-mips.c	Wed Oct 18 12:47:06 2000
*************** I_mips32,
*** 58,63 ****
--- 58,64 ----
  I_mips32_4k,
  I_mips5,
  I_mips64,
+ I_sb1,
  };
  
  
*************** static const bfd_arch_info_type arch_inf
*** 83,89 ****
    N (32, 32, bfd_mach_mips32,   "mips:mips32",   false, NN(I_mips32)),
    N (32, 32, bfd_mach_mips32_4k, "mips:mips32-4k", false, NN(I_mips32_4k)),
    N (64, 64, bfd_mach_mips5,    "mips:mips5", false, NN(I_mips5)),
!   N (64, 64, bfd_mach_mips64,   "mips:mips64", false, 0),
  };
  
  /* The default architecture is mips:3000, but with a machine number of
--- 84,91 ----
    N (32, 32, bfd_mach_mips32,   "mips:mips32",   false, NN(I_mips32)),
    N (32, 32, bfd_mach_mips32_4k, "mips:mips32-4k", false, NN(I_mips32_4k)),
    N (64, 64, bfd_mach_mips5,    "mips:mips5", false, NN(I_mips5)),
!   N (64, 64, bfd_mach_mips64,   "mips:mips64", false, NN(I_mips64)),
!   N (64, 64, bfd_mach_mips_sb1, "mips:sb1", false, 0),
  };
  
  /* The default architecture is mips:3000, but with a machine number of
diff -rcp ../src.P08/bfd/elf32-mips.c ./bfd/elf32-mips.c
*** ../src.P08/bfd/elf32-mips.c	Mon Oct 16 16:31:41 2000
--- ./bfd/elf32-mips.c	Wed Oct 18 12:48:23 2000
*************** elf_mips_mach (flags)
*** 1857,1862 ****
--- 1857,1865 ----
      case E_MIPS_MACH_MIPS32_4K:
        return bfd_mach_mips32_4k;
  
+     case E_MIPS_MACH_SB1:
+       return bfd_mach_mips_sb1;
+ 
      default:
        switch (flags & EF_MIPS_ARCH)
  	{
*************** _bfd_mips_elf_final_write_processing (ab
*** 2383,2388 ****
--- 2386,2395 ----
  
      case bfd_mach_mips64:
        val = E_MIPS_ARCH_64;
+       break;
+ 
+     case bfd_mach_mips_sb1:
+       val = E_MIPS_ARCH_64 | E_MIPS_MACH_SB1;
        break;
      }
  
diff -rcp ../src.P08/binutils/readelf.c ./binutils/readelf.c
*** ../src.P08/binutils/readelf.c	Mon Oct 16 16:32:04 2000
--- ./binutils/readelf.c	Wed Oct 18 12:49:01 2000
*************** get_machine_flags (e_flags, e_machine)
*** 1480,1485 ****
--- 1480,1486 ----
  	    case E_MIPS_MACH_4111: strcat (buf, ", 4111"); break;
  	    case E_MIPS_MACH_MIPS32_4K:
  				   strcat (buf, ", mips32-4k"); break;
+ 	    case E_MIPS_MACH_SB1:  strcat (buf, ", sb1"); break;
  	    }
  	  break;
  
diff -rcp ../src.P08/gas/config/tc-mips.c ./gas/config/tc-mips.c
*** ../src.P08/gas/config/tc-mips.c	Mon Oct 16 16:35:44 2000
--- ./gas/config/tc-mips.c	Wed Oct 18 12:50:27 2000
*************** MIPS options:\n\
*** 9244,9249 ****
--- 9244,9250 ----
    show (stream, "8000", &column, &first);
    show (stream, "10000", &column, &first);
    show (stream, "mips32-4k", &column, &first);
+   show (stream, "sb-1", &column, &first);
    fputc ('\n', stream);
  
    fprintf (stream, _("\
*************** static const struct mips_cpu_info mips_c
*** 12066,12071 ****
--- 12067,12078 ----
    { "mips32-4kc",	0,	ISA_MIPS32,	CPU_MIPS32_4K, },
    { "mips32-4km",	0,	ISA_MIPS32,	CPU_MIPS32_4K, },
    { "mips32-4kp",	0,	ISA_MIPS32,	CPU_MIPS32_4K, },
+ 
+   /* SiByte SB-1 CPU */
+   { "SB-1",		0,	ISA_MIPS64,	CPU_SB1, },
+   { "sb-1250",		0,	ISA_MIPS64,	CPU_SB1, },
+   { "sb1",		0,	ISA_MIPS64,	CPU_SB1, },
+   { "sb1250",		0,	ISA_MIPS64,	CPU_SB1, },
  
    /* End marker. */
    { NULL, 0, 0, 0, },
diff -rcp ../src.P08/gas/doc/as.texinfo ./gas/doc/as.texinfo
*** ../src.P08/gas/doc/as.texinfo	Mon Oct 16 16:37:01 2000
--- ./gas/doc/as.texinfo	Wed Oct 18 12:51:09 2000
*************** instructions around accesses to the @sam
*** 687,694 ****
  @samp{-no-m4650} turns off this option.
  
  @item -mcpu=@var{CPU}
! Generate code for a particular MIPS cpu.  This has little effect on the
! assembler, but it is passed by @code{@value{GCC}}.
  
  @cindex emulation
  @item --emulation=@var{name}
--- 687,695 ----
  @samp{-no-m4650} turns off this option.
  
  @item -mcpu=@var{CPU}
! Generate code for a particular MIPS cpu.  It is exactly equivalent to
! @samp{-m@var{cpu}}, except that there are more value of @var{cpu}
! understood.
  
  @cindex emulation
  @item --emulation=@var{name}
diff -rcp ../src.P08/gas/doc/c-mips.texi ./gas/doc/c-mips.texi
*** ../src.P08/gas/doc/c-mips.texi	Mon Oct 16 16:38:42 2000
--- ./gas/doc/c-mips.texi	Wed Oct 18 12:51:56 2000
*************** rm5721,
*** 149,155 ****
  rm7000,
  8000,
  10000,
! mips32-4k
  @end quotation
  
  
--- 149,156 ----
  rm7000,
  8000,
  10000,
! mips32-4k,
! sb1
  @end quotation
  
  
diff -rcp ../src.P08/include/elf/mips.h ./include/elf/mips.h
*** ../src.P08/include/elf/mips.h	Mon Oct 16 16:39:28 2000
--- ./include/elf/mips.h	Wed Oct 18 12:52:29 2000
*************** END_RELOC_NUMBERS (R_MIPS_maxext)
*** 163,168 ****
--- 163,169 ----
  #define E_MIPS_MACH_4650	0x00850000
  #define E_MIPS_MACH_4111	0x00880000
  #define E_MIPS_MACH_MIPS32_4K	0x00890000
+ #define E_MIPS_MACH_SB1		0x008a0000
  
  /* Processor specific section indices.  These sections do not actually
     exist.  Symbols with a st_shndx field corresponding to one of these
diff -rcp ../src.P08/include/opcode/mips.h ./include/opcode/mips.h
*** ../src.P08/include/opcode/mips.h	Mon Oct 16 16:40:24 2000
--- ./include/opcode/mips.h	Wed Oct 18 14:04:15 2000
*************** struct mips_opcode
*** 362,367 ****
--- 362,368 ----
  #define CPU_MIPS32_4K	3204113		/* 32, 04, octal 'K' */
  #define CPU_MIPS5	5
  #define CPU_MIPS64	64
+ #define CPU_SB1		12310201	/* octal 'SB', 01 */
  
  /* Test for membership in an ISA including chip specific ISAs.
     INSN is pointer to an element of the opcode table; ISA is the
diff -rcp ../src.P08/opcodes/mips-dis.c ./opcodes/mips-dis.c
*** ../src.P08/opcodes/mips-dis.c	Mon Oct 16 16:40:57 2000
--- ./opcodes/mips-dis.c	Wed Oct 18 12:53:35 2000
*************** set_mips_isa_type (mach, isa, cputype)
*** 373,378 ****
--- 373,382 ----
        target_processor = CPU_MIPS64;
        mips_isa = ISA_MIPS64;
        break;
+     case bfd_mach_mips_sb1:
+       target_processor = CPU_SB1;
+       mips_isa = ISA_MIPS64;
+       break;
      default:
        target_processor = CPU_R3000;
        mips_isa = ISA_MIPS3;


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