OPCODES: Add support for M340 processor

[Nick Clifton]

Hi Guys,

  As preparation for submitting the Cygnus version of the port of GCC
  to Motorola's M*Core processor, I am submitting (and applying!) the
  following patch to OPCODES to add support for the M*Core 340 part.

Cheers
	Nick

2000-02-10  Nick Clifton  <nickc@cygnus.com>

	* mcore-opc.h (enum mcore_opclass): Add MULSH and OPSR
	classes.
	(mcore_table): Add "idly4", "psrclr", "psrset", "mulsh" and
	"mulsh.h" instructions.
	* mcore-dis.c (imsk array): Add masks for MULSH and OPSR
	classes.
	(print_insn_mcore): Add support for little endian targets.
	Add support for MULSH and OPSR classes.

Index: opcodes/mcore-opc.h
===================================================================
RCS file: /cvs/src//src/opcodes/mcore-opc.h,v
retrieving revision 1.8
diff -p -r1.8 mcore-opc.h
*** mcore-opc.h	2000/01/21 00:27:29	1.8
--- mcore-opc.h	2000/02/10 21:36:24
*************** typedef enum
*** 24,29 ****
--- 24,30 ----
    OMa,   SI,   I7,   LS,   BR,    BL,    LR,    LJ,
    RM,    RQ,   JSR,  JMP,  OBRa,  OBRb,  OBRc,  OBR2,
    O1R1,  OMb,  OMc,  SIa,
+   MULSH, OPSR,
    JC,    JU,   JL,   RSI,  DO21,  OB2
  }
  mcore_opclass;
*************** mcore_opcode_info mcore_table[] =
*** 48,53 ****
--- 49,55 ----
    { "stop",	O0,	0,	0x0004 },
    { "wait",	O0,	0,	0x0005 },
    { "doze",	O0,	0,	0x0006 },
+   { "idly4",    O0,     0,      0x0007 },
    { "trap",	OT,	0,	0x0008 },
  /* SPACE:                       0x000C - 0x000F */
  /* SPACE:                       0x0010 - 0x001F */
*************** mcore_opcode_info mcore_table[] =
*** 99,104 ****
--- 101,108 ----
    { "tst",	O2,	0,	0x0E00 },
    { "cmpne",	O2,	0,	0x0F00 },
    { "mfcr",	OC,	0,	0x1000 },
+   { "psrclr",	OPSR,	0,	0x11F0 },
+   { "psrset",	OPSR,	0,	0x11F8 },
    { "mov",	O2,	0,	0x1200 },
    { "bgenr",	O2,	0,	0x1300 },
    { "rsub",	O2,	0,	0x1400 },
*************** mcore_opcode_info mcore_table[] =
*** 147,152 ****
--- 151,158 ----
    { "movi",	I7,	0,	0x6000 },
  #define MCORE_INST_BMASKI_ALT	0x6000
  #define MCORE_INST_BGENI_ALT	0x6000
+   { "mulsh",    MULSH,  0,      0x6800 },
+   { "muls.h",   MULSH,  0,      0x6800 },
  /* SPACE:                       0x6900 - 0x6FFF */
    { "jmpi",	LJ,	1,	0x7000 },
    { "jsri",	LJ,	0,	0x7F00 },

Index: opcodes/mcore-dis.c
===================================================================
RCS file: /cvs/src//src/opcodes/mcore-dis.c,v
retrieving revision 1.10
diff -p -r1.10 mcore-dis.c
*** mcore-dis.c	2000/01/20 19:08:43	1.10
--- mcore-dis.c	2000/02/10 21:36:24
*************** static const unsigned short imsk[] =
*** 57,62 ****
--- 57,65 ----
      /* OMc */ 0xFF00,
      /* SIa */ 0xFE00,
  
+   /* MULSH */ 0xFF00,    
+   /* OPSR  */ 0xFFF8,   /* psrset/psrclr */
+ 		 
      /* JC  */ 0,		/* JC,JU,JL don't appear in object */
      /* JU  */ 0,
      /* JL  */ 0,
*************** print_insn_mcore (memaddr, info)
*** 105,111 ****
--- 108,119 ----
        return -1;
      }
  
+   if (info->endian == BFD_ENDIAN_BIG)
      inst = (ibytes[0] << 8) | ibytes[1];
+   else if (info->endian == BFD_ENDIAN_LITTLE)
+     inst = (ibytes[1] << 8) | ibytes[0];
+   else
+     abort ();
  
    /* Just a linear search of the table.  */
    for (op = mcore_table; op->name != 0; op ++)
*************** print_insn_mcore (memaddr, info)
*** 129,134 ****
--- 137,143 ----
  	case JSR: fprintf (stream, "\t%s", name); break;
  	case OC:  fprintf (stream, "\t%s, %s", name, crname[(inst >> 4) & 0x1F]); break;
  	case O1R1: fprintf (stream, "\t%s, r1", name); break;
+ 	case MULSH:
  	case O2: fprintf (stream, "\t%s, %s", name, grname[(inst >> 4) & 0xF]); break;
  	case X1: fprintf (stream, "\tr1, %s", name); break;
  	case OI: fprintf (stream, "\t%s, %d", name, ((inst >> 4) & 0x1F) + 1); break;
*************** print_insn_mcore (memaddr, info)
*** 193,198 ****
--- 202,211 ----
  		break;
  	      }
  	    
+ 	    if (info->endian == BFD_ENDIAN_LITTLE)
+ 	      val = (ibytes[3] << 24) | (ibytes[2] << 16)
+ 		| (ibytes[1] << 8) | (ibytes[0]);
+ 	    else
  	      val = (ibytes[0] << 24) | (ibytes[1] << 16)
  		| (ibytes[2] << 8) | (ibytes[3]);
  	    
*************** print_insn_mcore (memaddr, info)
*** 218,223 ****
--- 231,240 ----
  		break;
  	      }
  
+ 	    if (info->endian == BFD_ENDIAN_LITTLE)
+ 	      val = (ibytes[3] << 24) | (ibytes[2] << 16)
+ 		| (ibytes[1] << 8) | (ibytes[0]);
+ 	    else
  	      val = (ibytes[0] << 24) | (ibytes[1] << 16)
  		| (ibytes[2] << 8) | (ibytes[3]);
  	    
*************** print_insn_mcore (memaddr, info)
*** 234,239 ****
--- 251,268 ----
  		fprintf (stream, "\t// from address pool at 0x%x",
  			 (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC);
  	      }
+ 	  }
+ 	  break;
+ 	  
+ 	case OPSR:
+ 	  {
+ 	    static char * fields[] = 
+ 	    {
+ 	      "af", "ie",    "fe",    "fe,ie", 
+ 	      "ee", "ee,ie", "ee,fe", "ee,fe,ie"
+ 	    };
+ 	    
+ 	    fprintf (stream, "\t%s", fields[inst & 0x7]);
  	  }
  	  break;