x86-64 support for gas part I
Jan Hubicka
jh@suse.cz
Sat Dec 16 14:49:00 GMT 2000
Hi
This patch adds all neccesary support to tc-i386.h and tc-i386.c to support
x86_64 architecture. It does not contain changes to instruction table and
configuration files to make the assembling working, but it is long and complex
as it is.
It seems to be quite hard to break it into smaller pieces, since majority of
changes is concerning adding new types Imm32S, Imm64, Disp32S and Disp32 that
are somehow unbreakable.
Other busy part is an support for extended registers - x86_64 defines
additional 8 integer registers, that are encoded using 16 different REX
prefixes. Also an IP relative addressing mode is added.
The code has been quite well tested - I am using i386 as regulary on my system
to build everything and get no problems and it passes the testsuite. On x86_64
this version of binutils builds the booting kernel.
Only drawback I am aware of is that the gas loses ability to print sane error
message when instruction is unsupported on given CPU. I am abusing the
cpu_flag to determine whether instructions is supported in the 32bit or 64bit
mode, in order to avoid new falg in the instruction template. Some
instructions (such as mov) are just partly supported in one of the modes, so
the test is not so easy - you need to pass the alternatives.
Honza
So pro 16 22:45:56 CET 2000 Jan Hubicka <jh@suse.cz>
* tc-i386.h (i386_target_format): Define even for ELFs.
(QWORD_MNEM_SUFFIX): New macro.
(CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags):
New macros
(CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber.
(IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix,
ImmExt): Renumber.
(Size64, No_qSuf, NoRex64, Rex64): New macros.
(Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
(Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,
InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc,
SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem):
Renumber.
(Reg, WordReg): Add Reg64.
(Imm): Add Imm32S and Imm64.
(EncImm): New.
(Disp): Add Disp64 and Disp32S.
(AnyMem): Add Disp32S.
(RegRex, RegRex64): New macros.
(rex_byte): New type.
* tc-i386.c (set_16bit_code_flag): Kill.
(fits_in_unsigned_long, fits_in_signed_long): New functions.
(reloc): New parameter "signed"; support x86_64.
(set_code_flag): New.
(DEFAULT_ARCH): New macro; default to "i386".
(default_arch): New static variable.
(struct _i386_insn): New fields Operand_PCrel; rex.
(flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT"
(flag_code): New enum and static variable.
(use_rela_relocations): New static variable.
(flag_code_names): New static variable.
(cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64.
(cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to
K6 and Athlon.
(i386_align_code): Return plain "nop" for x86_64.
(mode_from_disp_size): Support Disp32S.
(smallest_imm_type): Support Imm32S and Imm64.
(offset_in_range): Support size of 8.
(set_cpu_arch): Do not clobber to Cpu64/CpuNo64.
(md_pseudo_table): Add "code64"; use set_code_flat.
(md_begin): Emit sane error message on hash failure.
(tc_i386_fix_adjustable): Support x86_64 relocations.
(md_assemble): Support QWORD_MNEM_SUFFIX, REX registers,
instructions supported on particular arch just partially,
output of 64bit immediates, handling of Imm32S and Disp32S type.
(i386_immedaite): Support x86_64 relocations; support 64bit constants.
(i386_displacement): Likewise.
(i386_index_check): Cleanup; support 64bit addresses.
(md_apply_fix3): Support x86_64 relocation and rela.
(md_longopts): Add "32" and "64".
(md_parse_option): Add OPTION_32 and OPTION_64.
(i386_target_format): Call even for ELFs; choose between
elf64-x86-64 and elf32-i386.
(i386_validate_fix): Refuse GOTOFF in 64bit mode.
(tc_gen_reloc): Support rela relocations and x86_64.
(intel_e09_1): Support QWORD.
*** or/src/gas/config/tc-i386.c Sat Dec 16 13:21:12 2000
--- binutils/gas/config/tc-i386.c Sat Dec 16 22:44:12 2000
***************
*** 21,26 ****
--- 21,27 ----
/* Intel 80386 machine specific gas.
Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
+ x86_64 support by Jan Hubicka (jh@suse.cz)
Bugs & suggestions are completely welcome. This is free software.
Please help us make it better. */
*************** static int fits_in_signed_byte PARAMS ((
*** 55,73 ****
static int fits_in_unsigned_byte PARAMS ((offsetT));
static int fits_in_unsigned_word PARAMS ((offsetT));
static int fits_in_signed_word PARAMS ((offsetT));
static int smallest_imm_type PARAMS ((offsetT));
static offsetT offset_in_range PARAMS ((offsetT, int));
static int add_prefix PARAMS ((unsigned int));
! static void set_16bit_code_flag PARAMS ((int));
static void set_16bit_gcc_code_flag PARAMS ((int));
static void set_intel_syntax PARAMS ((int));
static void set_cpu_arch PARAMS ((int));
#ifdef BFD_ASSEMBLER
static bfd_reloc_code_real_type reloc
! PARAMS ((int, int, bfd_reloc_code_real_type));
#endif
/* 'md_assemble ()' gathers together information and puts it into a
i386_insn. */
--- 56,81 ----
static int fits_in_unsigned_byte PARAMS ((offsetT));
static int fits_in_unsigned_word PARAMS ((offsetT));
static int fits_in_signed_word PARAMS ((offsetT));
+ static int fits_in_unsigned_long PARAMS ((offsetT));
+ static int fits_in_signed_long PARAMS ((offsetT));
static int smallest_imm_type PARAMS ((offsetT));
static offsetT offset_in_range PARAMS ((offsetT, int));
static int add_prefix PARAMS ((unsigned int));
! static void set_code_flag PARAMS ((int));
static void set_16bit_gcc_code_flag PARAMS ((int));
static void set_intel_syntax PARAMS ((int));
static void set_cpu_arch PARAMS ((int));
#ifdef BFD_ASSEMBLER
static bfd_reloc_code_real_type reloc
! PARAMS ((int, int, int, bfd_reloc_code_real_type));
#endif
+ #ifndef DEFAULT_ARCH
+ #define DEFAULT_ARCH "i386"
+ #endif
+ static char *default_arch = DEFAULT_ARCH;
+
/* 'md_assemble ()' gathers together information and puts it into a
i386_insn. */
*************** struct _i386_insn
*** 103,108 ****
--- 111,120 ----
operand. */
union i386_op op[MAX_OPERANDS];
+ /* Flags for operands. */
+ unsigned int flags[MAX_OPERANDS];
+ #define Operand_PCrel 1
+
/* Relocation type for operand */
#ifdef BFD_ASSEMBLER
enum bfd_reloc_code_real disp_reloc[MAX_OPERANDS];
*************** struct _i386_insn
*** 129,134 ****
--- 141,147 ----
addressing modes of this insn are encoded. */
modrm_byte rm;
+ rex_byte rex;
sib_byte sib;
};
*************** static expressionS disp_expressions[2],
*** 220,228 ****
/* Current operand we are working on. */
static int this_operand;
! /* 1 if we're writing 16-bit code,
! 0 if 32-bit. */
! static int flag_16bit_code;
/* 1 for intel syntax,
0 if att syntax. */
--- 233,256 ----
/* Current operand we are working on. */
static int this_operand;
! /* We support four different modes. FLAG_CODE variable is used to distinguish
! these. */
!
! enum flag_code {
! CODE_32BIT,
! CODE_16BIT,
! CODE_64BIT };
!
! static enum flag_code flag_code;
! static int use_rela_relocations = 0;
!
! /* The names used to print error messages. */
! static const char *flag_code_names[] =
! {
! "32",
! "16",
! "64"
! };
/* 1 for intel syntax,
0 if att syntax. */
*************** static int quiet_warnings = 0;
*** 243,249 ****
static const char *cpu_arch_name = NULL;
/* CPU feature flags. */
! static unsigned int cpu_arch_flags = 0;
/* Interface to relax_segment.
There are 2 relax states for 386 jump insns: one for conditional &
--- 271,277 ----
static const char *cpu_arch_name = NULL;
/* CPU feature flags. */
! static unsigned int cpu_arch_flags = CpuUnknownFlags|CpuNo64;
/* Interface to relax_segment.
There are 2 relax states for 386 jump insns: one for conditional &
*************** static const arch_entry cpu_arch[] = {
*** 324,331 ****
{"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
{"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
{"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
! {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX|Cpu3dnow },
! {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|Cpu3dnow },
{NULL, 0 }
};
--- 352,360 ----
{"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
{"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
{"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
! {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
! {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow },
! {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE },
{NULL, 0 }
};
*************** i386_align_code (fragP, count)
*** 401,409 ****
f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
};
if (count > 0 && count <= 15)
{
! if (flag_16bit_code)
{
memcpy (fragP->fr_literal + fragP->fr_fix,
f16_patt[count - 1], count);
--- 430,443 ----
f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
};
+ /* ??? We can't use these fillers for x86_64, since they often kills the
+ upper halves. Solve later. */
+ if (flag_code == CODE_64BIT)
+ count = 1;
+
if (count > 0 && count <= 15)
{
! if (flag_code == CODE_16BIT)
{
memcpy (fragP->fr_literal + fragP->fr_fix,
f16_patt[count - 1], count);
*************** static INLINE unsigned int
*** 434,440 ****
mode_from_disp_size (t)
unsigned int t;
{
! return (t & Disp8) ? 1 : (t & (Disp16 | Disp32)) ? 2 : 0;
}
static INLINE int
--- 468,474 ----
mode_from_disp_size (t)
unsigned int t;
{
! return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
}
static INLINE int
*************** fits_in_signed_word (num)
*** 464,476 ****
{
return (-32768 <= num) && (num <= 32767);
}
static int
smallest_imm_type (num)
offsetT num;
{
! if (cpu_arch_flags != 0
! && cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486))
{
/* This code is disabled on the 486 because all the Imm1 forms
in the opcode table are slower on the i486. They're the
--- 498,530 ----
{
return (-32768 <= num) && (num <= 32767);
}
+ static INLINE int
+ fits_in_signed_long (num)
+ offsetT num;
+ {
+ #ifndef BFD64
+ return 1;
+ #else
+ return (((offsetT)((int)num)) == num);
+ #endif
+ } /* fits_in_signed_long() */
+ static INLINE int
+ fits_in_unsigned_long (num)
+ offsetT num;
+ {
+ #ifndef BFD64
+ return 1;
+ #else
+ return (num & 0xffffffff) == num;
+ #endif
+ } /* fits_in_unsigned_long() */
static int
smallest_imm_type (num)
offsetT num;
{
! if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64)
! && !(cpu_arch_flags & (CpuUnknown)))
{
/* This code is disabled on the 486 because all the Imm1 forms
in the opcode table are slower on the i486. They're the
*************** smallest_imm_type (num)
*** 478,492 ****
displacement, which has another syntax if you really want to
use that form. */
if (num == 1)
! return Imm1 | Imm8 | Imm8S | Imm16 | Imm32;
}
return (fits_in_signed_byte (num)
! ? (Imm8S | Imm8 | Imm16 | Imm32)
: fits_in_unsigned_byte (num)
! ? (Imm8 | Imm16 | Imm32)
: (fits_in_signed_word (num) || fits_in_unsigned_word (num))
! ? (Imm16 | Imm32)
! : (Imm32));
}
static offsetT
--- 532,550 ----
displacement, which has another syntax if you really want to
use that form. */
if (num == 1)
! return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
}
return (fits_in_signed_byte (num)
! ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
: fits_in_unsigned_byte (num)
! ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
: (fits_in_signed_word (num) || fits_in_unsigned_word (num))
! ? (Imm16 | Imm32 | Imm32S | Imm64)
! : fits_in_signed_long (num)
! ? (Imm32 | Imm32S | Imm64)
! : fits_in_unsigned_long (num)
! ? (Imm32 | Imm64)
! : Imm64);
}
static offsetT
*************** offset_in_range (val, size)
*** 501,512 ****
case 1: mask = ((addressT) 1 << 8) - 1; break;
case 2: mask = ((addressT) 1 << 16) - 1; break;
case 4: mask = ((addressT) 2 << 31) - 1; break;
default: abort ();
}
/* If BFD64, sign extend val. */
! if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
! val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
{
--- 559,574 ----
case 1: mask = ((addressT) 1 << 8) - 1; break;
case 2: mask = ((addressT) 1 << 16) - 1; break;
case 4: mask = ((addressT) 2 << 31) - 1; break;
+ #ifdef BFD64
+ case 8: mask = ((addressT) 2 << 63) - 1; break;
+ #endif
default: abort ();
}
/* If BFD64, sign extend val. */
! if (!use_rela_relocations)
! if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
! val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
{
*************** add_prefix (prefix)
*** 576,594 ****
}
static void
! set_16bit_code_flag (new_16bit_code_flag)
! int new_16bit_code_flag;
{
! flag_16bit_code = new_16bit_code_flag;
stackop_size = '\0';
}
static void
! set_16bit_gcc_code_flag (new_16bit_code_flag)
! int new_16bit_code_flag;
{
! flag_16bit_code = new_16bit_code_flag;
! stackop_size = new_16bit_code_flag ? 'l' : '\0';
}
static void
--- 638,668 ----
}
static void
! set_code_flag (value)
! int value;
{
! flag_code = value;
! cpu_arch_flags &= ~(Cpu64 | CpuNo64);
! cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
! if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
! {
! as_bad (_("64bit mode not supported on this CPU."));
! }
! if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
! {
! as_bad (_("64bit mode not supported on this CPU."));
! }
stackop_size = '\0';
}
static void
! set_16bit_gcc_code_flag (new_code_flag)
! int new_code_flag;
{
! flag_code = new_code_flag;
! cpu_arch_flags &= ~(Cpu64 | CpuNo64);
! cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
! stackop_size = 'l';
}
static void
*************** set_cpu_arch (dummy)
*** 647,653 ****
if (strcmp (string, cpu_arch[i].name) == 0)
{
cpu_arch_name = cpu_arch[i].name;
! cpu_arch_flags = cpu_arch[i].flags;
break;
}
}
--- 721,727 ----
if (strcmp (string, cpu_arch[i].name) == 0)
{
cpu_arch_name = cpu_arch[i].name;
! cpu_arch_flags = cpu_arch[i].flags | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
break;
}
}
*************** const pseudo_typeS md_pseudo_table[] =
*** 679,687 ****
{"value", cons, 2},
{"noopt", s_ignore, 0},
{"optim", s_ignore, 0},
! {"code16gcc", set_16bit_gcc_code_flag, 1},
! {"code16", set_16bit_code_flag, 1},
! {"code32", set_16bit_code_flag, 0},
{"intel_syntax", set_intel_syntax, 1},
{"att_syntax", set_intel_syntax, 0},
{"file", dwarf2_directive_file, 0},
--- 753,762 ----
{"value", cons, 2},
{"noopt", s_ignore, 0},
{"optim", s_ignore, 0},
! {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
! {"code16", set_code_flag, CODE_16BIT},
! {"code32", set_code_flag, CODE_32BIT},
! {"code64", set_code_flag, CODE_64BIT},
{"intel_syntax", set_intel_syntax, 1},
{"att_syntax", set_intel_syntax, 0},
{"file", dwarf2_directive_file, 0},
*************** md_begin ()
*** 729,735 ****
(PTR) core_optab);
if (hash_err)
{
- hash_error:
as_fatal (_("Internal Error: Can't hash %s: %s"),
(optab - 1)->name,
hash_err);
--- 804,809 ----
*************** md_begin ()
*** 753,759 ****
{
hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
if (hash_err)
! goto hash_error;
}
}
--- 827,835 ----
{
hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
if (hash_err)
! as_fatal (_("Internal Error: Can't hash %s: %s"),
! regtab->reg_name,
! hash_err);
}
}
*************** tc_i386_force_relocation (fixp)
*** 987,999 ****
}
#ifdef BFD_ASSEMBLER
- static bfd_reloc_code_real_type reloc
- PARAMS ((int, int, bfd_reloc_code_real_type));
static bfd_reloc_code_real_type
! reloc (size, pcrel, other)
int size;
int pcrel;
bfd_reloc_code_real_type other;
{
if (other != NO_RELOC)
--- 1066,1077 ----
}
#ifdef BFD_ASSEMBLER
static bfd_reloc_code_real_type
! reloc (size, pcrel, sign, other)
int size;
int pcrel;
+ int sign;
bfd_reloc_code_real_type other;
{
if (other != NO_RELOC)
*************** reloc (size, pcrel, other)
*** 1001,1006 ****
--- 1079,1086 ----
if (pcrel)
{
+ if (!sign)
+ as_bad(_("There are no unsigned pc-relative relocations"));
switch (size)
{
case 1: return BFD_RELOC_8_PCREL;
*************** reloc (size, pcrel, other)
*** 1011,1025 ****
}
else
{
! switch (size)
! {
! case 1: return BFD_RELOC_8;
! case 2: return BFD_RELOC_16;
! case 4: return BFD_RELOC_32;
! }
! as_bad (_("can not do %d byte relocation"), size);
}
return BFD_RELOC_NONE;
}
--- 1091,1114 ----
}
else
{
! if (sign)
! switch (size)
! {
! case 4: return BFD_RELOC_X86_64_32S;
! }
! else
! switch (size)
! {
! case 1: return BFD_RELOC_8;
! case 2: return BFD_RELOC_16;
! case 4: return BFD_RELOC_32;
! case 8: return BFD_RELOC_64;
! }
! as_bad (_("can not do %s %d byte relocation"),
! sign ? "signed" : "unsigned", size);
}
+ abort();
return BFD_RELOC_NONE;
}
*************** tc_i386_fix_adjustable (fixP)
*** 1043,1048 ****
--- 1132,1139 ----
if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
|| fixP->fx_r_type == BFD_RELOC_386_PLT32
|| fixP->fx_r_type == BFD_RELOC_386_GOT32
+ || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
+ || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
|| fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|| fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
return 0;
*************** tc_i386_fix_adjustable (fixP)
*** 1057,1062 ****
--- 1148,1155 ----
#define BFD_RELOC_386_PLT32 0
#define BFD_RELOC_386_GOT32 0
#define BFD_RELOC_386_GOTOFF 0
+ #define BFD_RELOC_X86_64_PLT32 0
+ #define BFD_RELOC_X86_64_GOT32 0
#endif
static int intel_float_operand PARAMS ((char *mnemonic));
*************** md_assemble (line)
*** 1153,1159 ****
Similarly, in 32-bit mode, do not allow addr32 or data32. */
if ((current_templates->start->opcode_modifier & (Size16 | Size32))
&& (((current_templates->start->opcode_modifier & Size32) != 0)
! ^ flag_16bit_code))
{
as_bad (_("redundant %s prefix"),
current_templates->start->name);
--- 1246,1252 ----
Similarly, in 32-bit mode, do not allow addr32 or data32. */
if ((current_templates->start->opcode_modifier & (Size16 | Size32))
&& (((current_templates->start->opcode_modifier & Size32) != 0)
! ^ (flag_code == CODE_16BIT)))
{
as_bad (_("redundant %s prefix"),
current_templates->start->name);
*************** md_assemble (line)
*** 1182,1187 ****
--- 1275,1281 ----
{
case WORD_MNEM_SUFFIX:
case BYTE_MNEM_SUFFIX:
+ case QWORD_MNEM_SUFFIX:
i.suffix = mnem_p[-1];
mnem_p[-1] = '\0';
current_templates = hash_find (op_hash, mnemonic);
*************** md_assemble (line)
*** 1219,1230 ****
/* Check if instruction is supported on specified architecture. */
if (cpu_arch_flags != 0)
{
! if (current_templates->start->cpu_flags & ~cpu_arch_flags)
! {
! as_warn (_("`%s' is not supported on `%s'"),
! current_templates->start->name, cpu_arch_name);
! }
! else if ((Cpu386 & ~cpu_arch_flags) && !flag_16bit_code)
{
as_warn (_("use .code16 to ensure correct addressing mode"));
}
--- 1313,1319 ----
/* Check if instruction is supported on specified architecture. */
if (cpu_arch_flags != 0)
{
! if ((Cpu386 & ~cpu_arch_flags) && !flag_code != CODE_16BIT)
{
as_warn (_("use .code16 to ensure correct addressing mode"));
}
*************** md_assemble (line)
*** 1394,1402 ****
union i386_op temp_op;
unsigned int temp_type;
#ifdef BFD_ASSEMBLER
! enum bfd_reloc_code_real temp_disp_reloc;
#else
! int temp_disp_reloc;
#endif
int xchg1 = 0;
int xchg2 = 0;
--- 1483,1491 ----
union i386_op temp_op;
unsigned int temp_type;
#ifdef BFD_ASSEMBLER
! enum bfd_reloc_code_real temp_reloc;
#else
! int temp_reloc;
#endif
int xchg1 = 0;
int xchg2 = 0;
*************** md_assemble (line)
*** 1417,1425 ****
temp_op = i.op[xchg2];
i.op[xchg2] = i.op[xchg1];
i.op[xchg1] = temp_op;
! temp_disp_reloc = i.disp_reloc[xchg2];
i.disp_reloc[xchg2] = i.disp_reloc[xchg1];
! i.disp_reloc[xchg1] = temp_disp_reloc;
if (i.mem_operands == 2)
{
--- 1506,1514 ----
temp_op = i.op[xchg2];
i.op[xchg2] = i.op[xchg1];
i.op[xchg1] = temp_op;
! temp_reloc = i.disp_reloc[xchg2];
i.disp_reloc[xchg2] = i.disp_reloc[xchg1];
! i.disp_reloc[xchg1] = temp_reloc;
if (i.mem_operands == 2)
{
*************** md_assemble (line)
*** 1452,1489 ****
guess_suffix = BYTE_MNEM_SUFFIX;
else if (i.types[op] & Reg16)
guess_suffix = WORD_MNEM_SUFFIX;
break;
}
}
! else if (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0))
guess_suffix = WORD_MNEM_SUFFIX;
for (op = i.operands; --op >= 0;)
! if ((i.types[op] & Imm)
! && i.op[op].imms->X_op == O_constant)
{
! /* If a suffix is given, this operand may be shortened. */
! switch (guess_suffix)
! {
! case WORD_MNEM_SUFFIX:
! i.types[op] |= Imm16;
! break;
! case BYTE_MNEM_SUFFIX:
! i.types[op] |= Imm16 | Imm8 | Imm8S;
! break;
! }
! /* If this operand is at most 16 bits, convert it to a
! signed 16 bit number before trying to see whether it will
! fit in an even smaller size. This allows a 16-bit operand
! such as $0xffe0 to be recognised as within Imm8S range. */
! if ((i.types[op] & Imm16)
! && (i.op[op].imms->X_add_number & ~(offsetT)0xffff) == 0)
! {
! i.op[op].imms->X_add_number =
! (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
}
- i.types[op] |= smallest_imm_type ((long) i.op[op].imms->X_add_number);
}
}
--- 1541,1622 ----
guess_suffix = BYTE_MNEM_SUFFIX;
else if (i.types[op] & Reg16)
guess_suffix = WORD_MNEM_SUFFIX;
+ else if (i.types[op] & Reg32)
+ guess_suffix = LONG_MNEM_SUFFIX;
+ else if (i.types[op] & Reg64)
+ guess_suffix = QWORD_MNEM_SUFFIX;
break;
}
}
! else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
guess_suffix = WORD_MNEM_SUFFIX;
for (op = i.operands; --op >= 0;)
! if (i.types[op] & Imm)
{
! switch (i.op[op].imms->X_op)
! {
! case O_constant:
! /* If a suffix is given, this operand may be shortened. */
! switch (guess_suffix)
! {
! case LONG_MNEM_SUFFIX:
! i.types[op] |= Imm32 | Imm64;
! break;
! case WORD_MNEM_SUFFIX:
! i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
! break;
! case BYTE_MNEM_SUFFIX:
! i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
! break;
! }
! /* If this operand is at most 16 bits, convert it to a
! signed 16 bit number before trying to see whether it will
! fit in an even smaller size. This allows a 16-bit operand
! such as $0xffe0 to be recognised as within Imm8S range. */
! if ((i.types[op] & Imm16)
! && (i.op[op].imms->X_add_number & ~(offsetT)0xffff) == 0)
! {
! i.op[op].imms->X_add_number =
! (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
! }
! if ((i.types[op] & Imm32)
! && (i.op[op].imms->X_add_number & ~(offsetT)0xffffffffU) == 0)
! {
! i.op[op].imms->X_add_number =
! (((i.op[op].imms->X_add_number & 0xffffffffU) ^ 0x80000000) - 0x80000000);
! }
! i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
! /* We must avoid matching of Imm32 templates when 64bit only immediate is available. */
! if (guess_suffix == QWORD_MNEM_SUFFIX)
! i.types[op] &= ~Imm32;
! break;
! case O_absent:
! case O_register:
! abort();
! /* Symbols and expressions. */
! default:
! /* Convert symbolic operand to proper sizes for matching. */
! switch (guess_suffix)
! {
! case QWORD_MNEM_SUFFIX:
! i.types[op] = Imm64 | Imm32S;
! break;
! case LONG_MNEM_SUFFIX:
! i.types[op] = Imm32 | Imm64;
! break;
! case WORD_MNEM_SUFFIX:
! i.types[op] = Imm16 | Imm32 | Imm64;
! break;
! break;
! case BYTE_MNEM_SUFFIX:
! i.types[op] = Imm8 | Imm8S | Imm16 | Imm32S | Imm32;
! break;
! break;
! }
! break;
}
}
}
*************** md_assemble (line)
*** 1507,1513 ****
disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
}
! if (fits_in_signed_byte (disp))
i.types[op] |= Disp8;
}
}
--- 1640,1661 ----
disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
}
! else if (i.types[op] & Disp32)
! {
! /* We know this operand is at most 32 bits, so convert to a
! signed 32 bit number before trying to see whether it will
! fit in an even smaller size. */
! disp = (((disp & 0xffffffff) ^ 0x80000000) - 0x80000000);
! }
! if (flag_code == CODE_64BIT)
! {
! if (fits_in_signed_long (disp))
! i.types[op] |= Disp32S;
! if (fits_in_unsigned_long (disp))
! i.types[op] |= Disp32;
! }
! if ((i.types[op] & (Disp32 | Disp32S | Disp16))
! && fits_in_signed_byte (disp))
i.types[op] |= Disp8;
}
}
*************** md_assemble (line)
*** 1524,1530 ****
? No_sSuf
: (i.suffix == LONG_MNEM_SUFFIX
? No_lSuf
! : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX ? No_xSuf : 0)))));
for (t = current_templates->start;
t < current_templates->end;
--- 1672,1680 ----
? No_sSuf
: (i.suffix == LONG_MNEM_SUFFIX
? No_lSuf
! : (i.suffix == QWORD_MNEM_SUFFIX
! ? No_qSuf
! : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX ? No_xSuf : 0))))));
for (t = current_templates->start;
t < current_templates->end;
*************** md_assemble (line)
*** 1585,1594 ****
/* found_reverse_match holds which of D or FloatDR
we've found. */
found_reverse_match = t->opcode_modifier & (D|FloatDR);
- break;
}
/* Found a forward 2 operand match here. */
! if (t->operands == 3)
{
/* Here we make use of the fact that there are no
reverse match 3 operand instructions, and all 3
--- 1735,1743 ----
/* found_reverse_match holds which of D or FloatDR
we've found. */
found_reverse_match = t->opcode_modifier & (D|FloatDR);
}
/* Found a forward 2 operand match here. */
! else if (t->operands == 3)
{
/* Here we make use of the fact that there are no
reverse match 3 operand instructions, and all 3
*************** md_assemble (line)
*** 1606,1611 ****
--- 1755,1765 ----
/* Found either forward/reverse 2 or 3 operand match here:
slip through to break. */
}
+ if (t->cpu_flags & ~cpu_arch_flags)
+ {
+ found_reverse_match = 0;
+ continue;
+ }
/* We've found a match; break out of loop. */
break;
}
*************** md_assemble (line)
*** 1690,1701 ****
}
}
/* If matched instruction specifies an explicit instruction mnemonic
suffix, use it. */
! if (i.tm.opcode_modifier & (Size16 | Size32))
{
if (i.tm.opcode_modifier & Size16)
i.suffix = WORD_MNEM_SUFFIX;
else
i.suffix = LONG_MNEM_SUFFIX;
}
--- 1844,1867 ----
}
}
+ if (i.reg_operands && flag_code < CODE_64BIT)
+ {
+ int op;
+ for (op = i.operands; --op >= 0; )
+ if ((i.types[op] & Reg)
+ && (i.op[op].regs->reg_flags & (RegRex64|RegRex)))
+ as_bad (_("Extended register `%%%s' available only in 64bit mode."),
+ i.op[op].regs->reg_name);
+ }
+
/* If matched instruction specifies an explicit instruction mnemonic
suffix, use it. */
! if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
{
if (i.tm.opcode_modifier & Size16)
i.suffix = WORD_MNEM_SUFFIX;
+ else if (i.tm.opcode_modifier & Size64)
+ i.suffix = QWORD_MNEM_SUFFIX;
else
i.suffix = LONG_MNEM_SUFFIX;
}
*************** md_assemble (line)
*** 1715,1720 ****
--- 1881,1887 ----
{
i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
(i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
+ (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
LONG_MNEM_SUFFIX);
break;
}
*************** md_assemble (line)
*** 1734,1739 ****
--- 1901,1907 ----
if (intel_syntax
&& (i.tm.base_opcode == 0xfb7
|| i.tm.base_opcode == 0xfb6
+ || i.tm.base_opcode == 0x63
|| i.tm.base_opcode == 0xfbe
|| i.tm.base_opcode == 0xfbf))
continue;
*************** md_assemble (line)
*** 1747,1752 ****
--- 1915,1927 ----
#endif
)
{
+ /* Prohibit these changes in the 64bit mode, since
+ the lowering is more complicated. */
+ if (flag_code == CODE_64BIT
+ && (i.tm.operand_types[op] & InOutPortReg) == 0)
+ as_bad (_("Incorect register `%%%s' used with`%c' suffix"),
+ i.op[op].regs->reg_name,
+ i.suffix);
#if REGISTER_WARNINGS
if (!quiet_warnings
&& (i.tm.operand_types[op] & InOutPortReg) == 0)
*************** md_assemble (line)
*** 1787,1804 ****
i.suffix);
return;
}
- #if REGISTER_WARNINGS
/* Warn if the e prefix on a general reg is missing. */
! else if (!quiet_warnings
&& (i.types[op] & Reg16) != 0
&& (i.tm.operand_types[op] & (Reg32|Acc)) != 0)
{
! as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
! (i.op[op].regs + 8)->reg_name,
! i.op[op].regs->reg_name,
! i.suffix);
! }
#endif
}
else if (i.suffix == WORD_MNEM_SUFFIX)
{
--- 1962,2024 ----
i.suffix);
return;
}
/* Warn if the e prefix on a general reg is missing. */
! else if ((!quiet_warnings || flag_code == CODE_64BIT)
&& (i.types[op] & Reg16) != 0
&& (i.tm.operand_types[op] & (Reg32|Acc)) != 0)
{
! /* Prohibit these changes in the 64bit mode, since
! the lowering is more complicated. */
! if (flag_code == CODE_64BIT)
! as_bad (_("Incorect register `%%%s' used with`%c' suffix"),
! i.op[op].regs->reg_name,
! i.suffix);
! #if REGISTER_WARNINGS
! else
! as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
! (i.op[op].regs + 8)->reg_name,
! i.op[op].regs->reg_name,
! i.suffix);
#endif
+ }
+ /* Warn if the r prefix on a general reg is missing. */
+ else if ((i.types[op] & Reg64) != 0
+ && (i.tm.operand_types[op] & (Reg32|Acc)) != 0)
+ {
+ as_bad (_("Incorect register `%%%s' used with`%c' suffix"),
+ i.op[op].regs->reg_name,
+ i.suffix);
+ }
+ }
+ else if (i.suffix == QWORD_MNEM_SUFFIX)
+ {
+ int op;
+ if (flag_code < CODE_64BIT)
+ as_bad (_("64bit operations available only in 64bit modes."));
+
+ for (op = i.operands; --op >= 0; )
+ /* Reject eight bit registers, except where the template
+ requires them. (eg. movzb) */
+ if ((i.types[op] & Reg8) != 0
+ && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0)
+ {
+ as_bad (_("`%%%s' not allowed with `%s%c'"),
+ i.op[op].regs->reg_name,
+ i.tm.name,
+ i.suffix);
+ return;
+ }
+ /* Warn if the e prefix on a general reg is missing. */
+ else if (((i.types[op] & Reg16) != 0
+ || (i.types[op] & Reg32) != 0)
+ && (i.tm.operand_types[op] & (Reg32|Acc)) != 0)
+ {
+ /* Prohibit these changes in the 64bit mode, since
+ the lowering is more complicated. */
+ as_bad (_("Incorect register `%%%s' used with`%c' suffix"),
+ i.op[op].regs->reg_name,
+ i.suffix);
+ }
}
else if (i.suffix == WORD_MNEM_SUFFIX)
{
*************** md_assemble (line)
*** 1815,1832 ****
i.suffix);
return;
}
- #if REGISTER_WARNINGS
/* Warn if the e prefix on a general reg is present. */
! else if (!quiet_warnings
&& (i.types[op] & Reg32) != 0
&& (i.tm.operand_types[op] & (Reg16|Acc)) != 0)
{
! as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
! (i.op[op].regs - 8)->reg_name,
! i.op[op].regs->reg_name,
! i.suffix);
! }
#endif
}
else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
/* Do nothing if the instruction is going to ignore the prefix. */
--- 2035,2059 ----
i.suffix);
return;
}
/* Warn if the e prefix on a general reg is present. */
! else if ((!quiet_warnings || flag_code == CODE_64BIT)
&& (i.types[op] & Reg32) != 0
&& (i.tm.operand_types[op] & (Reg16|Acc)) != 0)
{
! /* Prohibit these changes in the 64bit mode, since
! the lowering is more complicated. */
! if (flag_code == CODE_64BIT)
! as_bad (_("Incorect register `%%%s' used with`%c' suffix"),
! i.op[op].regs->reg_name,
! i.suffix);
! else
! #if REGISTER_WARNINGS
! as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
! (i.op[op].regs - 8)->reg_name,
! i.op[op].regs->reg_name,
! i.suffix);
#endif
+ }
}
else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
/* Do nothing if the instruction is going to ignore the prefix. */
*************** md_assemble (line)
*** 1838,1883 ****
{
i.suffix = stackop_size;
}
-
/* Make still unresolved immediate matches conform to size of immediate
given in i.suffix. Note: overlap2 cannot be an immediate! */
! if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32))
&& overlap0 != Imm8 && overlap0 != Imm8S
! && overlap0 != Imm16 && overlap0 != Imm32)
{
if (i.suffix)
{
overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) :
! (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : Imm32));
}
! else if (overlap0 == (Imm16 | Imm32))
{
overlap0 =
! (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32;
}
! else
{
as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
return;
}
}
! if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32))
&& overlap1 != Imm8 && overlap1 != Imm8S
! && overlap1 != Imm16 && overlap1 != Imm32)
{
if (i.suffix)
{
overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) :
! (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : Imm32));
}
! else if (overlap1 == (Imm16 | Imm32))
{
overlap1 =
! (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32;
}
! else
{
! as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
return;
}
}
--- 2065,2121 ----
{
i.suffix = stackop_size;
}
/* Make still unresolved immediate matches conform to size of immediate
given in i.suffix. Note: overlap2 cannot be an immediate! */
! if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S))
&& overlap0 != Imm8 && overlap0 != Imm8S
! && overlap0 != Imm16 && overlap0 != Imm32S
! && overlap0 != Imm32 && overlap0 != Imm64)
{
if (i.suffix)
{
overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) :
! (i.suffix == WORD_MNEM_SUFFIX ? Imm16 :
! (i.suffix == QWORD_MNEM_SUFFIX ? Imm64 | Imm32S : Imm32)));
}
! else if (overlap0 == (Imm16 | Imm32S | Imm32)
! || overlap0 == (Imm16 | Imm32)
! || overlap0 == (Imm16 | Imm32S))
{
overlap0 =
! ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32S;
}
! if (overlap0 != Imm8 && overlap0 != Imm8S
! && overlap0 != Imm16 && overlap0 != Imm32S
! && overlap0 != Imm32 && overlap0 != Imm64)
{
as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
return;
}
}
! if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32))
&& overlap1 != Imm8 && overlap1 != Imm8S
! && overlap1 != Imm16 && overlap1 != Imm32S
! && overlap1 != Imm32 && overlap1 != Imm64)
{
if (i.suffix)
{
overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) :
! (i.suffix == WORD_MNEM_SUFFIX ? Imm16 :
! (i.suffix == QWORD_MNEM_SUFFIX ? Imm64 | Imm32S : Imm32)));
}
! else if (overlap1 == (Imm16 | Imm32 | Imm32S)
! || overlap1 == (Imm16 | Imm32)
! || overlap1 == (Imm16 | Imm32S))
{
overlap1 =
! ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32S;
}
! if (overlap1 != Imm8 && overlap1 != Imm8S
! && overlap1 != Imm16 && overlap1 != Imm32S
! && overlap1 != Imm32 && overlap1 != Imm64)
{
! as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
return;
}
}
*************** md_assemble (line)
*** 1931,1937 ****
/* Now select between word & dword operations via the operand
size prefix, except for instructions that will ignore this
prefix anyway. */
! if ((i.suffix == LONG_MNEM_SUFFIX) == flag_16bit_code
&& !(i.tm.opcode_modifier & IgnoreSize))
{
unsigned int prefix = DATA_PREFIX_OPCODE;
--- 2169,2176 ----
/* Now select between word & dword operations via the operand
size prefix, except for instructions that will ignore this
prefix anyway. */
! if (i.suffix != QWORD_MNEM_SUFFIX
! && (i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
&& !(i.tm.opcode_modifier & IgnoreSize))
{
unsigned int prefix = DATA_PREFIX_OPCODE;
*************** md_assemble (line)
*** 1941,1946 ****
--- 2180,2191 ----
if (! add_prefix (prefix))
return;
}
+
+ /* Set mode64 for an operand. */
+ if (i.suffix == QWORD_MNEM_SUFFIX
+ && !(i.tm.opcode_modifier & NoRex64))
+ i.rex.mode64 = 1;
+
/* Size floating point instruction. */
if (i.suffix == LONG_MNEM_SUFFIX)
{
*************** md_assemble (line)
*** 1995,2000 ****
--- 2240,2247 ----
unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
/* Register goes in low 3 bits of opcode. */
i.tm.base_opcode |= i.op[op].regs->reg_num;
+ if (i.op[op].regs->reg_flags & RegRex)
+ i.rex.extZ=1;
if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
{
/* Warn about some common errors, but press on regardless.
*************** md_assemble (line)
*** 2045,2055 ****
--- 2292,2310 ----
{
i.rm.reg = i.op[dest].regs->reg_num;
i.rm.regmem = i.op[source].regs->reg_num;
+ if (i.op[dest].regs->reg_flags & RegRex)
+ i.rex.extX=1;
+ if (i.op[source].regs->reg_flags & RegRex)
+ i.rex.extZ=1;
}
else
{
i.rm.reg = i.op[source].regs->reg_num;
i.rm.regmem = i.op[dest].regs->reg_num;
+ if (i.op[dest].regs->reg_flags & RegRex)
+ i.rex.extZ=1;
+ if (i.op[source].regs->reg_flags & RegRex)
+ i.rex.extX=1;
}
}
else
*************** md_assemble (line)
*** 2071,2088 ****
if (! i.index_reg)
{
/* Operand is just <disp> */
! if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0))
{
i.rm.regmem = NO_BASE_REGISTER_16;
i.types[op] &= ~Disp;
i.types[op] |= Disp16;
}
! else
{
i.rm.regmem = NO_BASE_REGISTER;
i.types[op] &= ~Disp;
i.types[op] |= Disp32;
}
}
else /* ! i.base_reg && i.index_reg */
{
--- 2326,2355 ----
if (! i.index_reg)
{
/* Operand is just <disp> */
! if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
{
i.rm.regmem = NO_BASE_REGISTER_16;
i.types[op] &= ~Disp;
i.types[op] |= Disp16;
}
! else if (flag_code != CODE_64BIT)
{
i.rm.regmem = NO_BASE_REGISTER;
i.types[op] &= ~Disp;
i.types[op] |= Disp32;
}
+ else
+ {
+ /* 64bit mode overwrites the 32bit absolute addressing
+ by RIP relative addressing and absolute addressing
+ is encoded by one of the redundant SIB forms. */
+
+ i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
+ i.sib.base = NO_BASE_REGISTER;
+ i.sib.index = NO_INDEX_REGISTER;
+ i.types[op] &= ~Disp;
+ i.types[op] = Disp32S;
+ }
}
else /* ! i.base_reg && i.index_reg */
{
*************** md_assemble (line)
*** 2091,2099 ****
i.sib.scale = i.log2_scale_factor;
i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
i.types[op] &= ~Disp;
! i.types[op] |= Disp32; /* Must be 32 bit. */
}
}
else if (i.base_reg->reg_type & Reg16)
{
switch (i.base_reg->reg_num)
--- 2358,2379 ----
i.sib.scale = i.log2_scale_factor;
i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
i.types[op] &= ~Disp;
! if (flag_code != CODE_64BIT)
! i.types[op] = Disp32; /* Must be 32 bit */
! else
! i.types[op] |= Disp32S;
! if (i.index_reg->reg_flags & RegRex)
! i.rex.extY=1;
}
}
+ /* RIP addressing for 64bit mode. */
+ else if (i.base_reg->reg_type == BaseIndex)
+ {
+ i.rm.regmem = NO_BASE_REGISTER;
+ i.types[op] &= ~Disp;
+ i.types[op] = Disp32S;
+ i.flags[op] = Operand_PCrel;
+ }
else if (i.base_reg->reg_type & Reg16)
{
switch (i.base_reg->reg_num)
*************** md_assemble (line)
*** 2124,2134 ****
}
i.rm.mode = mode_from_disp_size (i.types[op]);
}
! else /* i.base_reg and 32 bit mode */
{
i.rm.regmem = i.base_reg->reg_num;
i.sib.base = i.base_reg->reg_num;
! if (i.base_reg->reg_num == EBP_REG_NUM)
{
default_seg = &ss;
if (i.disp_operands == 0)
--- 2404,2426 ----
}
i.rm.mode = mode_from_disp_size (i.types[op]);
}
! else /* i.base_reg and 32/64 bit mode */
{
+ if (flag_code == CODE_64BIT
+ && (i.types[op] & Disp))
+ {
+ if (i.types[op] & Disp8)
+ i.types[op] = Disp8 | Disp32S;
+ else
+ i.types[op] = Disp32S;
+ }
i.rm.regmem = i.base_reg->reg_num;
+ if (i.base_reg->reg_flags & RegRex)
+ i.rex.extZ=1;
i.sib.base = i.base_reg->reg_num;
! /* x86-64 ignores REX prefix bit here to avoid
! decoder complications. */
! if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
{
default_seg = &ss;
if (i.disp_operands == 0)
*************** md_assemble (line)
*** 2162,2167 ****
--- 2454,2461 ----
{
i.sib.index = i.index_reg->reg_num;
i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
+ if (i.index_reg->reg_flags & RegRex)
+ i.rex.extY=1;
}
i.rm.mode = mode_from_disp_size (i.types[op]);
}
*************** md_assemble (line)
*** 2204,2212 ****
/* If there is an extension opcode to put here, the
register number must be put into the regmem field. */
if (i.tm.extension_opcode != None)
! i.rm.regmem = i.op[op].regs->reg_num;
else
! i.rm.reg = i.op[op].regs->reg_num;
/* Now, if no memory operand has set i.rm.mode = 0, 1, 2
we must set it to 3 to indicate this is a register
--- 2498,2514 ----
/* If there is an extension opcode to put here, the
register number must be put into the regmem field. */
if (i.tm.extension_opcode != None)
! {
! i.rm.regmem = i.op[op].regs->reg_num;
! if (i.op[op].regs->reg_flags & RegRex)
! i.rex.extZ=1;
! }
else
! {
! i.rm.reg = i.op[op].regs->reg_num;
! if (i.op[op].regs->reg_flags & RegRex)
! i.rex.extX=1;
! }
/* Now, if no memory operand has set i.rm.mode = 0, 1, 2
we must set it to 3 to indicate this is a register
*************** md_assemble (line)
*** 2229,2234 ****
--- 2531,2538 ----
return;
}
i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
+ if (i.op[0].regs->reg_flags & RegRex)
+ i.rex.extZ=1;
}
else if ((i.tm.base_opcode & ~(D|W)) == MOV_AX_DISP32)
{
*************** md_assemble (line)
*** 2277,2282 ****
--- 2582,2630 ----
i.op[0].disps->X_op = O_symbol;
}
+ if (i.tm.opcode_modifier & Rex64)
+ i.rex.mode64 = 1;
+
+ /* For 8bit registers we would need an empty rex prefix.
+ Also in the case instruction is already having prefix,
+ we need to convert old registers to new ones. */
+
+ if (((i.types[0] & Reg8) && (i.op[0].regs->reg_flags & RegRex64))
+ || ((i.types[1] & Reg8) && (i.op[1].regs->reg_flags & RegRex64))
+ || ((i.rex.mode64 || i.rex.extX || i.rex.extY || i.rex.extZ || i.rex.empty)
+ && ((i.types[0] & Reg8) || (i.types[1] & Reg8))))
+ {
+ int x;
+ i.rex.empty=1;
+ for (x = 0; x < 2; x++)
+ {
+ /* Look for 8bit operand that does use old registers. */
+ if (i.types[x] & Reg8
+ && !(i.op[x].regs->reg_flags & RegRex64))
+ {
+ /* In case it is "hi" register, give up. */
+ if (i.op[x].regs->reg_num > 3)
+ as_bad (_("Can't encode registers '%%%s' in the instruction requiring REX prefix.\n"),
+ i.op[x].regs->reg_name);
+
+ /* Otherwise it is equivalent to the extended register.
+ Since the encoding don't change this is merely cosmetical
+ cleanup for debug output. */
+
+ i.op[x].regs = i.op[x].regs + 8;
+ }
+ }
+ }
+
+ if (i.rex.mode64 || i.rex.extX || i.rex.extY || i.rex.extZ || i.rex.empty)
+ i.rex.byte = (0x40
+ | (i.rex.mode64 ? 8 : 0)
+ | (i.rex.extX ? 4 : 0)
+ | (i.rex.extY ? 2 : 0)
+ | (i.rex.extZ ? 1 : 0));
+ else
+ i.rex.byte = 0;
+
/* We are ready to output the insn. */
{
register char *p;
*************** md_assemble (line)
*** 2289,2295 ****
int prefix;
code16 = 0;
! if (flag_16bit_code)
code16 = CODE16;
prefix = 0;
--- 2637,2643 ----
int prefix;
code16 = 0;
! if (flag_code == CODE_16BIT)
code16 = CODE16;
prefix = 0;
*************** md_assemble (line)
*** 2299,2304 ****
--- 2647,2654 ----
i.prefixes -= 1;
code16 ^= CODE16;
}
+ if (i.rex.byte)
+ prefix++;
size = 4;
if (code16)
*************** md_assemble (line)
*** 2316,2323 ****
insn_size += prefix + 1;
/* Prefix and 1 opcode byte go in fr_fix. */
p = frag_more (prefix + 1);
! if (prefix)
*p++ = DATA_PREFIX_OPCODE;
*p = i.tm.base_opcode;
/* 1 possible extra opcode + displacement go in var part.
Pass reloc in fr_var. */
--- 2666,2675 ----
insn_size += prefix + 1;
/* Prefix and 1 opcode byte go in fr_fix. */
p = frag_more (prefix + 1);
! if (i.prefix[DATA_PREFIX])
*p++ = DATA_PREFIX_OPCODE;
+ if (i.rex.byte)
+ *p++ = i.rex.byte;
*p = i.tm.base_opcode;
/* 1 possible extra opcode + displacement go in var part.
Pass reloc in fr_var. */
*************** md_assemble (line)
*** 2351,2357 ****
int code16;
code16 = 0;
! if (flag_16bit_code)
code16 = CODE16;
if (i.prefix[DATA_PREFIX])
--- 2703,2709 ----
int code16;
code16 = 0;
! if (flag_code == CODE_16BIT)
code16 = CODE16;
if (i.prefix[DATA_PREFIX])
*************** md_assemble (line)
*** 2370,2375 ****
--- 2722,2733 ----
if (i.prefixes != 0 && !intel_syntax)
as_warn (_("skipping prefixes on this instruction"));
+ if (i.rex.byte)
+ {
+ FRAG_APPEND_1_CHAR (i.rex.byte);
+ insn_size++;
+ }
+
if (fits_in_unsigned_byte (i.tm.base_opcode))
{
insn_size += 1 + size;
*************** md_assemble (line)
*** 2385,2391 ****
*p++ = i.tm.base_opcode & 0xff;
fix_new_exp (frag_now, p - frag_now->fr_literal, size,
! i.op[0].disps, 1, reloc (size, 1, i.disp_reloc[0]));
}
else if (i.tm.opcode_modifier & JumpInterSegment)
{
--- 2743,2749 ----
*p++ = i.tm.base_opcode & 0xff;
fix_new_exp (frag_now, p - frag_now->fr_literal, size,
! i.op[0].disps, 1, reloc (size, 1, 1, i.disp_reloc[0]));
}
else if (i.tm.opcode_modifier & JumpInterSegment)
{
*************** md_assemble (line)
*** 2394,2400 ****
int code16;
code16 = 0;
! if (flag_16bit_code)
code16 = CODE16;
prefix = 0;
--- 2752,2758 ----
int code16;
code16 = 0;
! if (flag_code == CODE_16BIT)
code16 = CODE16;
prefix = 0;
*************** md_assemble (line)
*** 2404,2409 ****
--- 2762,2769 ----
i.prefixes -= 1;
code16 ^= CODE16;
}
+ if (i.rex.byte)
+ prefix++;
size = 4;
if (code16)
*************** md_assemble (line)
*** 2415,2422 ****
/* 1 opcode; 2 segment; offset */
insn_size += prefix + 1 + 2 + size;
p = frag_more (prefix + 1 + 2 + size);
! if (prefix)
*p++ = DATA_PREFIX_OPCODE;
*p++ = i.tm.base_opcode;
if (i.op[1].imms->X_op == O_constant)
{
--- 2775,2787 ----
/* 1 opcode; 2 segment; offset */
insn_size += prefix + 1 + 2 + size;
p = frag_more (prefix + 1 + 2 + size);
!
! if (i.prefix[DATA_PREFIX])
*p++ = DATA_PREFIX_OPCODE;
+
+ if (i.rex.byte)
+ *p++ = i.rex.byte;
+
*p++ = i.tm.base_opcode;
if (i.op[1].imms->X_op == O_constant)
{
*************** md_assemble (line)
*** 2433,2439 ****
}
else
fix_new_exp (frag_now, p - frag_now->fr_literal, size,
! i.op[1].imms, 0, reloc (size, 0, i.disp_reloc[0]));
if (i.op[0].imms->X_op != O_constant)
as_bad (_("can't handle non absolute segment in `%s'"),
i.tm.name);
--- 2798,2804 ----
}
else
fix_new_exp (frag_now, p - frag_now->fr_literal, size,
! i.op[1].imms, 0, reloc (size, 0, 0, i.disp_reloc[0]));
if (i.op[0].imms->X_op != O_constant)
as_bad (_("can't handle non absolute segment in `%s'"),
i.tm.name);
*************** md_assemble (line)
*** 2457,2462 ****
--- 2822,2830 ----
}
}
+ if (i.rex.byte)
+ FRAG_APPEND_1_CHAR (i.rex.byte), insn_size++;
+
/* Now the opcode; be careful about word order here! */
if (fits_in_unsigned_byte (i.tm.base_opcode))
{
*************** md_assemble (line)
*** 2531,2541 ****
offsetT val;
size = 4;
! if (i.types[n] & (Disp8 | Disp16))
{
size = 2;
if (i.types[n] & Disp8)
size = 1;
}
val = offset_in_range (i.op[n].disps->X_add_number,
size);
--- 2899,2911 ----
offsetT val;
size = 4;
! if (i.types[n] & (Disp8 | Disp16 | Disp64))
{
size = 2;
if (i.types[n] & Disp8)
size = 1;
+ if (i.types[n] & Disp64)
+ size = 8;
}
val = offset_in_range (i.op[n].disps->X_add_number,
size);
*************** md_assemble (line)
*** 2546,2560 ****
else
{
int size = 4;
! if (i.types[n] & Disp16)
! size = 2;
insn_size += size;
p = frag_more (size);
fix_new_exp (frag_now, p - frag_now->fr_literal, size,
! i.op[n].disps, 0,
! reloc (size, 0, i.disp_reloc[n]));
}
}
}
--- 2916,2966 ----
else
{
int size = 4;
+ int sign = 0;
+ int pcrel = (i.flags[n] & Operand_PCrel) != 0;
+
+ /* The PC relative address is computed relative
+ to the instruction boundary, so in case immediate
+ fields follows, we need to adjust the value. */
+ if (pcrel && i.imm_operands)
+ {
+ int imm_size = 4;
+ register unsigned int n1;
! for (n1 = 0; n1 < i.operands; n1++)
! if (i.types[n1] & Imm)
! {
! if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
! {
! imm_size = 2;
! if (i.types[n1] & (Imm8 | Imm8S))
! imm_size = 1;
! if (i.types[n1] & Imm64)
! imm_size = 8;
! }
! break;
! }
! /* We should find the immediate. */
! if (n1 == i.operands)
! abort();
! i.op[n].disps->X_add_number -= imm_size;
! }
!
! if (i.types[n] & Disp32S)
! sign = 1;
!
! if (i.types[n1] & (Disp16 | Disp64))
! {
! size = 2;
! if (i.types[n] & Disp64)
! size = 8;
! }
insn_size += size;
p = frag_more (size);
fix_new_exp (frag_now, p - frag_now->fr_literal, size,
! i.op[n].disps, pcrel,
! reloc (size, pcrel, sign, i.disp_reloc[n]));
}
}
}
*************** md_assemble (line)
*** 2575,2585 ****
offsetT val;
size = 4;
! if (i.types[n] & (Imm8 | Imm8S | Imm16))
{
size = 2;
if (i.types[n] & (Imm8 | Imm8S))
size = 1;
}
val = offset_in_range (i.op[n].imms->X_add_number,
size);
--- 2981,2993 ----
offsetT val;
size = 4;
! if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
{
size = 2;
if (i.types[n] & (Imm8 | Imm8S))
size = 1;
+ else if (i.types[n] & Imm64)
+ size = 8;
}
val = offset_in_range (i.op[n].imms->X_add_number,
size);
*************** md_assemble (line)
*** 2599,2613 ****
int reloc_type;
#endif
int size = 4;
! if (i.types[n] & Imm16)
! size = 2;
! else if (i.types[n] & (Imm8 | Imm8S))
! size = 1;
insn_size += size;
p = frag_more (size);
! reloc_type = reloc (size, 0, i.disp_reloc[0]);
#ifdef BFD_ASSEMBLER
if (reloc_type == BFD_RELOC_32
&& GOT_symbol
--- 3007,3029 ----
int reloc_type;
#endif
int size = 4;
+ int sign = 0;
! if ((i.types[n] & (Imm32S))
! && i.suffix == QWORD_MNEM_SUFFIX)
! sign = 1;
! if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
! {
! size = 2;
! if (i.types[n] & (Imm8 | Imm8S))
! size = 1;
! if (i.types[n] & Imm64)
! size = 8;
! }
insn_size += size;
p = frag_more (size);
! reloc_type = reloc (size, 0, sign, i.disp_reloc[0]);
#ifdef BFD_ASSEMBLER
if (reloc_type == BFD_RELOC_32
&& GOT_symbol
*************** md_assemble (line)
*** 2618,2623 ****
--- 3034,3042 ----
(i.op[n].imms->X_op_symbol)->X_op)
== O_subtract))))
{
+ /* We don't support dynamic linking on x86-64 yet. */
+ if (flag_code == CODE_64BIT)
+ abort();
reloc_type = BFD_RELOC_386_GOTPC;
i.op[n].imms->X_add_number += 3;
}
*************** i386_immediate (imm_start)
*** 2682,2688 ****
int first;
/* GOT relocations are not supported in 16 bit mode. */
! if (flag_16bit_code)
as_bad (_("GOT relocations not supported in 16 bit mode"));
if (GOT_symbol == NULL)
--- 3101,3107 ----
int first;
/* GOT relocations are not supported in 16 bit mode. */
! if (flag_code == CODE_16BIT)
as_bad (_("GOT relocations not supported in 16 bit mode"));
if (GOT_symbol == NULL)
*************** i386_immediate (imm_start)
*** 2690,2706 ****
if (strncmp (cp + 1, "PLT", 3) == 0)
{
! i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32;
len = 3;
}
else if (strncmp (cp + 1, "GOTOFF", 6) == 0)
{
i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF;
len = 6;
}
else if (strncmp (cp + 1, "GOT", 3) == 0)
{
! i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32;
len = 3;
}
else
--- 3109,3141 ----
if (strncmp (cp + 1, "PLT", 3) == 0)
{
! if (flag_code == CODE_64BIT)
! i.disp_reloc[this_operand] = BFD_RELOC_X86_64_PLT32;
! else
! i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32;
len = 3;
}
else if (strncmp (cp + 1, "GOTOFF", 6) == 0)
{
+ if (flag_code == CODE_64BIT)
+ as_bad ("GOTOFF relocations are unsupported in 64bit mode.");
i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF;
len = 6;
}
else if (strncmp (cp + 1, "GOT", 3) == 0)
{
! if (flag_code == CODE_64BIT)
! i.disp_reloc[this_operand] = BFD_RELOC_X86_64_GOT32;
! else
! i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32;
! len = 3;
! }
! else if (strncmp (cp + 1, "GOTPCREL", 3) == 0)
! {
! if (flag_code == CODE_64BIT)
! i.disp_reloc[this_operand] = BFD_RELOC_X86_64_GOTPCREL;
! else
! as_bad ("GOTPCREL relocations are supported only in 64bit mode.");
len = 3;
}
else
*************** i386_immediate (imm_start)
*** 2736,2746 ****
exp->X_add_symbol = (symbolS *) 0;
exp->X_op_symbol = (symbolS *) 0;
}
!
! if (exp->X_op == O_constant)
{
/* Size it properly later. */
! i.types[this_operand] |= Imm32;
}
#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
else if (1
--- 3171,3184 ----
exp->X_add_symbol = (symbolS *) 0;
exp->X_op_symbol = (symbolS *) 0;
}
! else if (exp->X_op == O_constant)
{
/* Size it properly later. */
! i.types[this_operand] |= Imm64;
! /* If BFD64, sign extend val. */
! if (!use_rela_relocations)
! if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
! exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
}
#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
else if (1
*************** i386_immediate (imm_start)
*** 2768,2777 ****
{
/* This is an address. The size of the address will be
determined later, depending on destination register,
! suffix, or the default for the section. We exclude
! Imm8S here so that `push $foo' and other instructions
! with an Imm8S form will use Imm16 or Imm32. */
! i.types[this_operand] |= (Imm8 | Imm16 | Imm32);
}
return 1;
--- 3206,3213 ----
{
/* This is an address. The size of the address will be
determined later, depending on destination register,
! suffix, or the default for the section. */
! i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
}
return 1;
*************** i386_displacement (disp_start, disp_end)
*** 2830,2837 ****
char *save_input_line_pointer;
int bigdisp = Disp32;
! if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0))
bigdisp = Disp16;
i.types[this_operand] |= bigdisp;
exp = &disp_expressions[i.disp_operands];
--- 3266,3275 ----
char *save_input_line_pointer;
int bigdisp = Disp32;
! if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
bigdisp = Disp16;
+ if (flag_code == CODE_64BIT)
+ bigdisp = Disp64;
i.types[this_operand] |= bigdisp;
exp = &disp_expressions[i.disp_operands];
*************** i386_displacement (disp_start, disp_end)
*** 2901,2907 ****
int first;
/* GOT relocations are not supported in 16 bit mode. */
! if (flag_16bit_code)
as_bad (_("GOT relocations not supported in 16 bit mode"));
if (GOT_symbol == NULL)
--- 3339,3345 ----
int first;
/* GOT relocations are not supported in 16 bit mode. */
! if (flag_code == CODE_16BIT)
as_bad (_("GOT relocations not supported in 16 bit mode"));
if (GOT_symbol == NULL)
*************** i386_displacement (disp_start, disp_end)
*** 2909,2925 ****
if (strncmp (cp + 1, "PLT", 3) == 0)
{
! i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32;
len = 3;
}
else if (strncmp (cp + 1, "GOTOFF", 6) == 0)
{
i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF;
len = 6;
}
else if (strncmp (cp + 1, "GOT", 3) == 0)
{
! i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32;
len = 3;
}
else
--- 3347,3378 ----
if (strncmp (cp + 1, "PLT", 3) == 0)
{
! if (flag_code == CODE_64BIT)
! i.disp_reloc[this_operand] = BFD_RELOC_X86_64_PLT32;
! else
! i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32;
len = 3;
}
else if (strncmp (cp + 1, "GOTOFF", 6) == 0)
{
+ if (flag_code == CODE_64BIT)
+ as_bad ("GOTOFF relocation is not supported in 64bit mode.");
i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF;
len = 6;
}
else if (strncmp (cp + 1, "GOT", 3) == 0)
{
! if (flag_code == CODE_64BIT)
! i.disp_reloc[this_operand] = BFD_RELOC_X86_64_GOT32;
! else
! i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32;
! len = 3;
! }
! else if (strncmp (cp + 1, "GOTPCREL", 3) == 0)
! {
! if (flag_code != CODE_64BIT)
! as_bad ("GOTPCREL relocation is supported only in 64bit mode.");
! i.disp_reloc[this_operand] = BFD_RELOC_X86_64_GOTPCREL;
len = 3;
}
else
*************** i386_displacement (disp_start, disp_end)
*** 2943,2949 ****
/* We do this to make sure that the section symbol is in
the symbol table. We will ultimately change the relocation
to be relative to the beginning of the section. */
! if (i.disp_reloc[this_operand] == BFD_RELOC_386_GOTOFF)
{
if (S_IS_LOCAL(exp->X_add_symbol)
&& S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
--- 3396,3403 ----
/* We do this to make sure that the section symbol is in
the symbol table. We will ultimately change the relocation
to be relative to the beginning of the section. */
! if (i.disp_reloc[this_operand] == BFD_RELOC_386_GOTOFF
! || i.disp_reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
{
if (S_IS_LOCAL(exp->X_add_symbol)
&& S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
*************** i386_displacement (disp_start, disp_end)
*** 2994,2999 ****
--- 3448,3455 ----
return 0;
}
#endif
+ else if (flag_code == CODE_64BIT)
+ i.types[this_operand] |= Disp32S | Disp32;
return 1;
}
*************** static int
*** 3006,3037 ****
i386_index_check (operand_string)
const char *operand_string;
{
#if INFER_ADDR_PREFIX
int fudged = 0;
tryprefix:
#endif
! if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0)
! /* 16 bit mode checks. */
! ? ((i.base_reg
! && ((i.base_reg->reg_type & (Reg16|BaseIndex))
! != (Reg16|BaseIndex)))
! || (i.index_reg
! && (((i.index_reg->reg_type & (Reg16|BaseIndex))
! != (Reg16|BaseIndex))
! || ! (i.base_reg
! && i.base_reg->reg_num < 6
! && i.index_reg->reg_num >= 6
! && i.log2_scale_factor == 0))))
! /* 32 bit mode checks. */
! : ((i.base_reg
! && (i.base_reg->reg_type & Reg32) == 0)
! || (i.index_reg
! && ((i.index_reg->reg_type & (Reg32|BaseIndex))
! != (Reg32|BaseIndex)))))
{
#if INFER_ADDR_PREFIX
! if (i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0')
{
i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
i.prefixes += 1;
--- 3462,3519 ----
i386_index_check (operand_string)
const char *operand_string;
{
+ int ok;
#if INFER_ADDR_PREFIX
int fudged = 0;
tryprefix:
#endif
! ok = 1;
! if (flag_code == CODE_64BIT)
! {
! /* 64bit checks. */
! if ((i.base_reg
! && ((i.base_reg->reg_type & Reg64) == 0)
! && (i.base_reg->reg_type != BaseIndex
! || i.index_reg))
! || (i.index_reg
! && ((i.index_reg->reg_type & (Reg64|BaseIndex))
! != (Reg64|BaseIndex))))
! ok = 0;
! }
! else
! {
! if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
! {
! /* 16bit checks. */
! if ((i.base_reg
! && ((i.base_reg->reg_type & (Reg16|BaseIndex|RegRex))
! != (Reg16|BaseIndex)))
! || (i.index_reg
! && (((i.index_reg->reg_type & (Reg16|BaseIndex))
! != (Reg16|BaseIndex))
! || ! (i.base_reg
! && i.base_reg->reg_num < 6
! && i.index_reg->reg_num >= 6
! && i.log2_scale_factor == 0))))
! ok = 0;
! }
! else
! {
! /* 32bit checks. */
! if ((i.base_reg
! && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
! || (i.index_reg
! && ((i.index_reg->reg_type & (Reg32|BaseIndex|RegRex))
! != (Reg32|BaseIndex))))
! ok = 0;
! }
! }
! if (!ok)
{
#if INFER_ADDR_PREFIX
! if (flag_code != CODE_64BIT
! && i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0')
{
i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
i.prefixes += 1;
*************** i386_index_check (operand_string)
*** 3052,3058 ****
#endif
as_bad (_("`%s' is not a valid %s bit base/index expression"),
operand_string,
! flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0) ? "16" : "32");
return 0;
}
return 1;
--- 3534,3540 ----
#endif
as_bad (_("`%s' is not a valid %s bit base/index expression"),
operand_string,
! flag_code_names[flag_code]);
return 0;
}
return 1;
*************** md_apply_fix3 (fixP, valp, seg)
*** 3651,3656 ****
--- 4133,4139 ----
switch (fixP->fx_r_type)
{
case BFD_RELOC_386_PLT32:
+ case BFD_RELOC_X86_64_PLT32:
/* Make the jump instruction point to the address of the operand. At
runtime we merely add the offset to the actual PLT entry. */
value = -4;
*************** md_apply_fix3 (fixP, valp, seg)
*** 3698,3706 ****
--- 4181,4191 ----
value -= 1;
break;
case BFD_RELOC_386_GOT32:
+ case BFD_RELOC_X86_64_GOT32:
value = 0; /* Fully resolved at runtime. No addend. */
break;
case BFD_RELOC_386_GOTOFF:
+ case BFD_RELOC_X86_64_GOTPCREL:
break;
case BFD_RELOC_VTABLE_INHERIT:
*************** md_apply_fix3 (fixP, valp, seg)
*** 3714,3720 ****
--- 4199,4218 ----
#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
*valp = value;
#endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
+
+ #ifndef BFD_ASSEMBLER
md_number_to_chars (p, value, fixP->fx_size);
+ #else
+ /* Are we finished with this relocation now? */
+ if (fixP->fx_addsy == 0 && fixP->fx_pcrel == 0)
+ fixP->fx_done = 1;
+ else if (use_rela_relocations)
+ {
+ fixP->fx_no_overflow = 1;
+ value = 0;
+ }
+ md_number_to_chars (p, value, fixP->fx_size);
+ #endif
return 1;
}
*************** const char *md_shortopts = "kVQ:sq";
*** 3859,3864 ****
--- 4357,4366 ----
const char *md_shortopts = "q";
#endif
struct option md_longopts[] = {
+ #define OPTION_32 (OPTION_MD_BASE + 0)
+ {"32", no_argument, NULL, OPTION_32},
+ #define OPTION_64 (OPTION_MD_BASE + 1)
+ {"64", no_argument, NULL, OPTION_64},
{NULL, no_argument, NULL, 0}
};
size_t md_longopts_size = sizeof (md_longopts);
*************** md_parse_option (c, arg)
*** 3894,3899 ****
--- 4396,4429 ----
.stab instead of .stab.excl. We always use .stab anyhow. */
break;
#endif
+ #ifdef OBJ_ELF
+ case OPTION_32:
+ case OPTION_64:
+ {
+ const char **list, **l;
+
+ default_arch = c == OPTION_32 ? "i386" : "x86_64";
+ list = bfd_target_list ();
+ for (l = list; *l != NULL; l++)
+ {
+ if (c == OPTION_32)
+ {
+ if (strcmp (*l, "elf32-i386") == 0)
+ break;
+ }
+ else
+ {
+ if (strcmp (*l, "elf64-x86-64") == 0)
+ break;
+ }
+ }
+ if (*l == NULL)
+ as_fatal (_("No compiled in support for %d bit object file format"),
+ c == OPTION_32 ? 32 : 64);
+ free (list);
+ }
+ break;
+ #endif
default:
return 0;
*************** md_show_usage (stream)
*** 3921,3933 ****
#ifdef BFD_ASSEMBLER
#if ((defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_COFF)) \
|| (defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_AOUT)) \
! || (defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)))
/* Pick the target format to use. */
const char *
i386_target_format ()
{
switch (OUTPUT_FLAVOR)
{
#ifdef OBJ_MAYBE_AOUT
--- 4451,4470 ----
#ifdef BFD_ASSEMBLER
#if ((defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_COFF)) \
|| (defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_AOUT)) \
! || (defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT))) \
! || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
/* Pick the target format to use. */
const char *
i386_target_format ()
{
+ if (!strcmp (default_arch, "x86_64"))
+ set_code_flag (CODE_64BIT);
+ else if (!strcmp (default_arch, "i386"))
+ set_code_flag (CODE_32BIT);
+ else
+ as_fatal (_("Unknown architecture"));
switch (OUTPUT_FLAVOR)
{
#ifdef OBJ_MAYBE_AOUT
*************** i386_target_format ()
*** 3938,3946 ****
case bfd_target_coff_flavour:
return "coff-i386";
#endif
! #ifdef OBJ_MAYBE_ELF
case bfd_target_elf_flavour:
! return "elf32-i386";
#endif
default:
abort ();
--- 4475,4487 ----
case bfd_target_coff_flavour:
return "coff-i386";
#endif
! #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
case bfd_target_elf_flavour:
! {
! if (flag_code == CODE_64BIT)
! use_rela_relocations = 1;
! return flag_code == CODE_64BIT ? "elf64-x86-64" : "elf32-i386";
! }
#endif
default:
abort ();
*************** i386_validate_fix (fixp)
*** 4033,4038 ****
--- 4574,4582 ----
{
if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
{
+ /* GOTOFF relocation are nonsense in 64bit mode. */
+ if (flag_code == CODE_64BIT)
+ abort();
fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
fixp->fx_subsy = 0;
}
*************** tc_gen_reloc (section, fixp)
*** 4048,4057 ****
--- 4592,4605 ----
switch (fixp->fx_r_type)
{
+ case BFD_RELOC_X86_64_PLT32:
+ case BFD_RELOC_X86_64_GOT32:
+ case BFD_RELOC_X86_64_GOTPCREL:
case BFD_RELOC_386_PLT32:
case BFD_RELOC_386_GOT32:
case BFD_RELOC_386_GOTOFF:
case BFD_RELOC_386_GOTPC:
+ case BFD_RELOC_X86_64_32S:
case BFD_RELOC_RVA:
case BFD_RELOC_VTABLE_ENTRY:
case BFD_RELOC_VTABLE_INHERIT:
*************** tc_gen_reloc (section, fixp)
*** 4083,4088 ****
--- 4631,4637 ----
case 1: code = BFD_RELOC_8; break;
case 2: code = BFD_RELOC_16; break;
case 4: code = BFD_RELOC_32; break;
+ case 8: code = BFD_RELOC_64; break;
}
}
break;
*************** tc_gen_reloc (section, fixp)
*** 4091,4112 ****
if (code == BFD_RELOC_32
&& GOT_symbol
&& fixp->fx_addsy == GOT_symbol)
! code = BFD_RELOC_386_GOTPC;
rel = (arelent *) xmalloc (sizeof (arelent));
rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
*rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
! /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
! vtable entry to be used in the relocation's section offset. */
! if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
! rel->address = fixp->fx_offset;
! if (fixp->fx_pcrel)
! rel->addend = fixp->fx_addnumber;
else
! rel->addend = 0;
rel->howto = bfd_reloc_type_lookup (stdoutput, code);
if (rel->howto == NULL)
--- 4640,4686 ----
if (code == BFD_RELOC_32
&& GOT_symbol
&& fixp->fx_addsy == GOT_symbol)
! {
! /* We don't support GOTPC on 64bit targets. */
! if (flag_code == CODE_64BIT)
! abort();
! code = BFD_RELOC_386_GOTPC;
! }
rel = (arelent *) xmalloc (sizeof (arelent));
rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
*rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
! if (!use_rela_relocations)
! {
! /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
! vtable entry to be used in the relocation's section offset. */
! if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
! rel->address = fixp->fx_offset;
! if (fixp->fx_pcrel)
! rel->addend = fixp->fx_addnumber;
! else
! rel->addend = 0;
! }
! /* Use the rela in 64bit mode. */
else
! {
! rel->addend = fixp->fx_offset;
! #ifdef OBJ_ELF
! /* Ohhh, this is ugly. The problem is that if this is a local global
! symbol, the relocation will entirely be performed at link time, not
! at assembly time. bfd_perform_reloc doesn't know about this sort
! of thing, and as a result we need to fake it out here. */
! if ((S_IS_EXTERN (fixp->fx_addsy) || S_IS_WEAK (fixp->fx_addsy))
! && !S_IS_COMMON(fixp->fx_addsy))
! rel->addend -= symbol_get_bfdsym (fixp->fx_addsy)->value;
! #endif
! if (fixp->fx_pcrel)
! rel->addend -= fixp->fx_size;
! }
!
rel->howto = bfd_reloc_type_lookup (stdoutput, code);
if (rel->howto == NULL)
*************** intel_e09_1 ()
*** 4564,4574 ****
if (intel_parser.got_a_float == 1) /* "f..." */
i.suffix = LONG_MNEM_SUFFIX;
else
! {
! as_bad (_("operand modifier `%s' supported only for i387 operations\n"),
! prev_token.str);
! return 0;
! }
}
else if (prev_token.code == T_XWORD)
--- 5135,5141 ----
if (intel_parser.got_a_float == 1) /* "f..." */
i.suffix = LONG_MNEM_SUFFIX;
else
! i.suffix = QWORD_MNEM_SUFFIX;
}
else if (prev_token.code == T_XWORD)
*** or/src/gas/config/tc-i386.h Thu Dec 7 18:46:22 2000
--- binutils/gas/config/tc-i386.h Sat Dec 16 23:08:50 2000
*************** extern int tc_i386_fix_adjustable PARAMS
*** 103,109 ****
#if ((defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_COFF)) \
|| (defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_AOUT)) \
! || (defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)))
extern const char *i386_target_format PARAMS ((void));
#define TARGET_FORMAT i386_target_format ()
#else
--- 103,110 ----
#if ((defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_COFF)) \
|| (defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_AOUT)) \
! || (defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT))) \
! || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
extern const char *i386_target_format PARAMS ((void));
#define TARGET_FORMAT i386_target_format ()
#else
*************** extern const char extra_symbol_chars[];
*** 229,234 ****
--- 230,236 ----
#define BYTE_MNEM_SUFFIX 'b'
#define SHORT_MNEM_SUFFIX 's'
#define LONG_MNEM_SUFFIX 'l'
+ #define QWORD_MNEM_SUFFIX 'q'
/* Intel Syntax */
#define LONG_DOUBLE_MNEM_SUFFIX 'x'
*************** typedef struct
*** 278,286 ****
#define Cpu486 0x10 /* i486 or better required */
#define Cpu586 0x20 /* i585 or better required */
#define Cpu686 0x40 /* i686 or better required */
! #define CpuMMX 0x80 /* MMX support required */
! #define CpuSSE 0x100 /* Streaming SIMD extensions required */
! #define Cpu3dnow 0x200 /* 3dnow! support required */
/* the bits in opcode_modifier are used to generate the final opcode from
the base_opcode. These bits also are used to detect alternate forms of
--- 280,299 ----
#define Cpu486 0x10 /* i486 or better required */
#define Cpu586 0x20 /* i585 or better required */
#define Cpu686 0x40 /* i686 or better required */
! #define CpuK6 0x80 /* AMD K6 or better required*/
! #define CpuAthlon 0x100 /* AMD Athlon or better required*/
! #define CpuSledgehammer 0x200 /* Sledgehammer or better required */
! #define CpuMMX 0x400 /* MMX support required */
! #define CpuSSE 0x800 /* Streaming SIMD extensions required */
! #define Cpu3dnow 0x1000 /* 3dnow! support required */
! #define CpuUnknown 0x2000 /* The CPU is unknown, be on the safe side. */
!
! /* These flags are set by gas depending on the flag_code. */
! #define Cpu64 0x4000000 /* 64bit support required */
! #define CpuNo64 0x8000000 /* Not supported in the 64bit mode */
!
! /* The default value for unknown CPUs - enable all features to avoid problems. */
! #define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuSledgehammer|CpuMMX|CpuSSE|Cpu3dnow)
/* the bits in opcode_modifier are used to generate the final opcode from
the base_opcode. These bits also are used to detect alternate forms of
*************** typedef struct
*** 305,323 ****
#define Seg3ShortForm 0x1000 /* fs/gs segment register insns. */
#define Size16 0x2000 /* needs size prefix if in 32-bit mode */
#define Size32 0x4000 /* needs size prefix if in 16-bit mode */
! #define IgnoreSize 0x8000 /* instruction ignores operand size prefix */
! #define DefaultSize 0x10000 /* default insn size depends on mode */
! #define No_bSuf 0x20000 /* b suffix on instruction illegal */
! #define No_wSuf 0x40000 /* w suffix on instruction illegal */
! #define No_lSuf 0x80000 /* l suffix on instruction illegal */
! #define No_sSuf 0x100000 /* s suffix on instruction illegal */
! #define No_xSuf 0x200000 /* x suffix on instruction illegal */
! #define FWait 0x400000 /* instruction needs FWAIT */
! #define IsString 0x800000 /* quick test for string instructions */
! #define regKludge 0x1000000 /* fake an extra reg operand for clr, imul */
! #define IsPrefix 0x2000000 /* opcode is a prefix */
! #define ImmExt 0x4000000 /* instruction has extension in 8 bit imm */
! #define Ugh 0x8000000 /* deprecated fp insn, gets a warning */
/* operand_types[i] describes the type of operand i. This is made
by OR'ing together all of the possible type masks. (e.g.
--- 318,340 ----
#define Seg3ShortForm 0x1000 /* fs/gs segment register insns. */
#define Size16 0x2000 /* needs size prefix if in 32-bit mode */
#define Size32 0x4000 /* needs size prefix if in 16-bit mode */
! #define Size64 0x8000 /* needs size prefix if in 16-bit mode */
! #define IgnoreSize 0x10000 /* instruction ignores operand size prefix */
! #define DefaultSize 0x20000 /* default insn size depends on mode */
! #define No_bSuf 0x40000 /* b suffix on instruction illegal */
! #define No_wSuf 0x80000 /* w suffix on instruction illegal */
! #define No_lSuf 0x100000 /* l suffix on instruction illegal */
! #define No_sSuf 0x200000 /* s suffix on instruction illegal */
! #define No_qSuf 0x400000 /* q suffix on instruction illegal */
! #define No_xSuf 0x800000 /* x suffix on instruction illegal */
! #define FWait 0x1000000 /* instruction needs FWAIT */
! #define IsString 0x2000000 /* quick test for string instructions */
! #define regKludge 0x4000000 /* fake an extra reg operand for clr, imul */
! #define IsPrefix 0x8000000 /* opcode is a prefix */
! #define ImmExt 0x10000000 /* instruction has extension in 8 bit imm */
! #define NoRex64 0x20000000 /* instruction don't need Rex64 prefix. */
! #define Rex64 0x40000000 /* instruction require Rex64 prefix. */
! #define Ugh 0x80000000 /* deprecated fp insn, gets a warning */
/* operand_types[i] describes the type of operand i. This is made
by OR'ing together all of the possible type masks. (e.g.
*************** typedef struct
*** 330,380 ****
#define Reg8 0x1 /* 8 bit reg */
#define Reg16 0x2 /* 16 bit reg */
#define Reg32 0x4 /* 32 bit reg */
/* immediate */
! #define Imm8 0x8 /* 8 bit immediate */
! #define Imm8S 0x10 /* 8 bit immediate sign extended */
! #define Imm16 0x20 /* 16 bit immediate */
! #define Imm32 0x40 /* 32 bit immediate */
! #define Imm1 0x80 /* 1 bit immediate */
/* memory */
! #define BaseIndex 0x100
/* Disp8,16,32 are used in different ways, depending on the
instruction. For jumps, they specify the size of the PC relative
displacement, for baseindex type instructions, they specify the
size of the offset relative to the base register, and for memory
offset instructions such as `mov 1234,%al' they specify the size of
the offset relative to the segment base. */
! #define Disp8 0x200 /* 8 bit displacement */
! #define Disp16 0x400 /* 16 bit displacement */
! #define Disp32 0x800 /* 32 bit displacement */
/* specials */
! #define InOutPortReg 0x1000 /* register to hold in/out port addr = dx */
! #define ShiftCount 0x2000 /* register to hold shift cound = cl */
! #define Control 0x4000 /* Control register */
! #define Debug 0x8000 /* Debug register */
! #define Test 0x10000 /* Test register */
! #define FloatReg 0x20000 /* Float register */
! #define FloatAcc 0x40000 /* Float stack top %st(0) */
! #define SReg2 0x80000 /* 2 bit segment register */
! #define SReg3 0x100000 /* 3 bit segment register */
! #define Acc 0x200000 /* Accumulator %al or %ax or %eax */
! #define JumpAbsolute 0x400000
! #define RegMMX 0x800000 /* MMX register */
! #define RegXMM 0x1000000 /* XMM registers in PIII */
! #define EsSeg 0x2000000 /* String insn operand with fixed es segment */
/* InvMem is for instructions with a modrm byte that only allow a
general register encoding in the i.tm.mode and i.tm.regmem fields,
eg. control reg moves. They really ought to support a memory form,
but don't, so we add an InvMem flag to the register operand to
indicate that it should be encoded in the i.tm.regmem field. */
! #define InvMem 0x4000000
! #define Reg (Reg8|Reg16|Reg32) /* gen'l register */
! #define WordReg (Reg16|Reg32)
#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
! #define Imm (Imm8|Imm8S|Imm16|Imm32) /* gen'l immediate */
! #define Disp (Disp8|Disp16|Disp32) /* General displacement */
! #define AnyMem (Disp|BaseIndex|InvMem) /* General memory */
/* The following aliases are defined because the opcode table
carefully specifies the allowed memory types for each instruction.
At the moment we can only tell a memory reference size by the
--- 347,404 ----
#define Reg8 0x1 /* 8 bit reg */
#define Reg16 0x2 /* 16 bit reg */
#define Reg32 0x4 /* 32 bit reg */
+ #define Reg64 0x8 /* 64 bit reg */
/* immediate */
! #define Imm8 0x10 /* 8 bit immediate */
! #define Imm8S 0x20 /* 8 bit immediate sign extended */
! #define Imm16 0x40 /* 16 bit immediate */
! #define Imm32 0x80 /* 32 bit immediate */
! #define Imm32S 0x100 /* 32 bit immediate sign extended */
! #define Imm64 0x200 /* 64 bit immediate */
! #define Imm1 0x400 /* 1 bit immediate */
/* memory */
! #define BaseIndex 0x800
/* Disp8,16,32 are used in different ways, depending on the
instruction. For jumps, they specify the size of the PC relative
displacement, for baseindex type instructions, they specify the
size of the offset relative to the base register, and for memory
offset instructions such as `mov 1234,%al' they specify the size of
the offset relative to the segment base. */
! #define Disp8 0x1000 /* 8 bit displacement */
! #define Disp16 0x2000 /* 16 bit displacement */
! #define Disp32 0x4000 /* 32 bit displacement */
! #define Disp32S 0x8000 /* 32 bit signed displacement */
! #define Disp64 0x10000 /* 64 bit displacement */
/* specials */
! #define InOutPortReg 0x20000 /* register to hold in/out port addr = dx */
! #define ShiftCount 0x40000 /* register to hold shift cound = cl */
! #define Control 0x80000 /* Control register */
! #define Debug 0x100000 /* Debug register */
! #define Test 0x200000 /* Test register */
! #define FloatReg 0x400000 /* Float register */
! #define FloatAcc 0x800000 /* Float stack top %st(0) */
! #define SReg2 0x1000000 /* 2 bit segment register */
! #define SReg3 0x2000000 /* 3 bit segment register */
! #define Acc 0x4000000 /* Accumulator %al or %ax or %eax */
! #define JumpAbsolute 0x8000000
! #define RegMMX 0x10000000 /* MMX register */
! #define RegXMM 0x20000000 /* XMM registers in PIII */
! #define EsSeg 0x40000000 /* String insn operand with fixed es segment */
!
/* InvMem is for instructions with a modrm byte that only allow a
general register encoding in the i.tm.mode and i.tm.regmem fields,
eg. control reg moves. They really ought to support a memory form,
but don't, so we add an InvMem flag to the register operand to
indicate that it should be encoded in the i.tm.regmem field. */
! #define InvMem 0x80000000
! #define Reg (Reg8|Reg16|Reg32|Reg64) /* gen'l register */
! #define WordReg (Reg16|Reg32|Reg64)
#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
! #define Imm (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */
! #define EncImm (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */
! #define Disp (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */
! #define AnyMem (Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem) /* General memory */
/* The following aliases are defined because the opcode table
carefully specifies the allowed memory types for each instruction.
At the moment we can only tell a memory reference size by the
*************** typedef struct
*** 408,413 ****
--- 432,440 ----
{
char *reg_name;
unsigned int reg_type;
+ unsigned int reg_flags;
+ #define RegRex 0x1 /* Extended register. */
+ #define RegRex64 0x2 /* Extended 8 bit register. */
unsigned int reg_num;
}
reg_entry;
*************** typedef struct
*** 427,432 ****
--- 454,471 ----
unsigned int mode; /* how to interpret regmem & reg */
}
modrm_byte;
+
+ /* x86-64 extension prefix. */
+ typedef struct
+ {
+ unsigned int mode64;
+ unsigned int extX; /* Used to extend modrm reg field. */
+ unsigned int extY; /* Used to extend SIB index field. */
+ unsigned int extZ; /* Used to extend modrm reg/mem, SIB base, modrm base fields. */
+ unsigned int empty; /* Used to old-style byte registers to new style. */
+ unsigned char byte;
+ }
+ rex_byte;
/* 386 opcode byte to code indirect addressing. */
typedef struct
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