[binutils-gdb] RISC-V: Add support for XAndesBFHCvt extension
Kuan-Lin Chen
kuanlinchen@sourceware.org
Tue Sep 1 03:04:29 GMT 2026
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=ce6455998599d6a8af6f4aea8813392921e4e86c
commit ce6455998599d6a8af6f4aea8813392921e4e86c
Author: Ethan Y. C. Liang <ycl669@andestech.com>
Date: Tue Nov 18 17:13:44 2025 +0800
RISC-V: Add support for XAndesBFHCvt extension
Spec: https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add support for
XAndesBFHCvt extension.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* doc/c-riscv.texi: Note XAndesBFHCvt as an additional ISA extension for
Andes.
* testsuite/gas/riscv/march-help.l: Add xandesbfhcvt string.
* testsuite/gas/riscv/x-andes-bfhcvt.d: New test.
* testsuite/gas/riscv/x-andes-bfhcvt.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h: Add corresponding MATCH and MASK instruction
opcode macros.
* opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_XANDESBFHCVT.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcode): Add scalar BF16 and FP32 conversion
instructions.
Signed-off-by: Ethan Y. C. Liang <ycl669@andestech.com>
Diff:
---
bfd/elfxx-riscv.c | 5 +++++
gas/doc/c-riscv.texi | 5 +++++
gas/testsuite/gas/riscv/march-help.l | 1 +
gas/testsuite/gas/riscv/x-andes-bfhcvt.d | 12 ++++++++++++
gas/testsuite/gas/riscv/x-andes-bfhcvt.s | 3 +++
include/opcode/riscv-opc.h | 8 ++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 4 ++++
8 files changed, 39 insertions(+)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 73924a73207..d69323bd439 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1652,6 +1652,7 @@ static const struct riscv_supported_ext riscv_supported_std_zxm_ext[] =
static const struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
{
+ {"xandesbfhcvt", ISA_SPEC_CLASS_DRAFT, 5, 0, 0 },
{"xcvalu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xcvbi", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xcvbitmanip", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -3086,6 +3087,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "svinval");
case INSN_CLASS_H:
return riscv_subset_supports (rps, "h");
+ case INSN_CLASS_XANDESBFHCVT:
+ return riscv_subset_supports (rps, "xandesbfhcvt");
case INSN_CLASS_XCVALU:
return riscv_subset_supports (rps, "xcvalu");
case INSN_CLASS_XCVBI:
@@ -3432,6 +3435,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return "svinval";
case INSN_CLASS_H:
return _("h");
+ case INSN_CLASS_XANDESBFHCVT:
+ return "xandesbfhcvt";
case INSN_CLASS_XCVALU:
return "xcvalu";
case INSN_CLASS_XCVBI:
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 5ed877cbfc5..bae96c9b624 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -766,6 +766,11 @@ extensions supported and provides the location of their
publicly-released documentation:
@table @r
+@item XAndesBFHCvt
+The XAndesBFHCvt extension provides scalar BF16 and FP32 conversion instructions.
+
+It is documented in @url{https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf}.
+
@item XCvAlu
The XCvAlu extension provides instructions for general ALU operations.
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index 142369b6b1d..494433e21ce 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -167,6 +167,7 @@ All available -march extensions for RISC-V:
smmpm 1.0
sspm 1.0
supm 1.0
+ xandesbfhcvt 5.0
xcvalu 1.0
xcvbi 1.0
xcvbitmanip 1.0
diff --git a/gas/testsuite/gas/riscv/x-andes-bfhcvt.d b/gas/testsuite/gas/riscv/x-andes-bfhcvt.d
new file mode 100644
index 00000000000..c22d3f18df0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-andes-bfhcvt.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xandesbfhcvt
+#source: x-andes-bfhcvt.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+00b1455b[ ]+nds\.fcvt\.s\.bf16[ ]+fa0,fa1
+[ ]+[0-9a-f]+:[ ]+00b1c55b[ ]+nds\.fcvt\.bf16\.s[ ]+fa0,fa1
diff --git a/gas/testsuite/gas/riscv/x-andes-bfhcvt.s b/gas/testsuite/gas/riscv/x-andes-bfhcvt.s
new file mode 100644
index 00000000000..293da84d370
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-andes-bfhcvt.s
@@ -0,0 +1,3 @@
+target:
+ nds.fcvt.s.bf16 fa0, fa1
+ nds.fcvt.bf16.s fa0, fa1
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 6ce4b4b1a0b..13fe74f851f 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2601,6 +2601,11 @@
#define MASK_VFQWBDOTA_ALT_VV 0xfc00707f
#define MATCH_VFBDOTA_VV 0xac001077
#define MASK_VFBDOTA_VV 0xfc00707f
+/* Vendor-specific (Andes) XAndesBFHCvt instructions. */
+#define MATCH_NDS_FCVT_S_BF16 0x1405b
+#define MASK_NDS_FCVT_S_BF16 0xfe0ff07f
+#define MATCH_NDS_FCVT_BF16_S 0x1c05b
+#define MASK_NDS_FCVT_BF16_S 0xfe0ff07f
/* Vendor-specific (CORE-V) Xcvmac instructions. */
#define MATCH_CV_MAC 0x9000302b
#define MASK_CV_MAC 0xfe00707f
@@ -5043,6 +5048,9 @@ DECLARE_INSN(sd_rl, MATCH_SDR, MASK_SDR)
DECLARE_INSN(sctrclr, MATCH_SCTRCLR, MASK_SCTRCLR)
/* Smrnmi instruction */
DECLARE_INSN(mnret, MATCH_MNRET, MASK_MNRET)
+/* Vendor-specific (Andes) XAndesBFHCvt instructions. */
+DECLARE_INSN(nds_fcvt_s_bf16, MATCH_NDS_FCVT_S_BF16, MASK_NDS_FCVT_S_BF16)
+DECLARE_INSN(nds_fcvt_bf16_s, MATCH_NDS_FCVT_BF16_S, MASK_NDS_FCVT_BF16_S)
/* Vendor-specific (T-Head) XTheadBa instructions. */
DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
/* Vendor-specific (T-Head) XTheadBb instructions. */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 7c24988ac4b..a22007f5c59 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -606,6 +606,7 @@ enum riscv_insn_class
INSN_CLASS_ZACAS,
INSN_CLASS_ZABHA_AND_ZACAS,
INSN_CLASS_H,
+ INSN_CLASS_XANDESBFHCVT,
INSN_CLASS_XCVALU,
INSN_CLASS_XCVBI,
INSN_CLASS_XCVBITMANIP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 617b444697e..d43a889f219 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2349,6 +2349,10 @@ const struct riscv_opcode riscv_opcodes[] =
{"hsv.w", 0, INSN_CLASS_H, "t,0(s)", MATCH_HSV_W, MASK_HSV_W, match_opcode, INSN_DREF|INSN_4_BYTE },
{"hsv.d", 64, INSN_CLASS_H, "t,0(s)", MATCH_HSV_D, MASK_HSV_D, match_opcode, INSN_DREF|INSN_8_BYTE },
+/* Vendor-specific (Andes) XAndesBFHCvt instructions. */
+{"nds.fcvt.s.bf16", 0, INSN_CLASS_XANDESBFHCVT, "D,T", MATCH_NDS_FCVT_S_BF16, MASK_NDS_FCVT_S_BF16, match_opcode, 0},
+{"nds.fcvt.bf16.s", 0, INSN_CLASS_XANDESBFHCVT, "D,T", MATCH_NDS_FCVT_BF16_S, MASK_NDS_FCVT_BF16_S, match_opcode, 0},
+
/* Vendor-specific (CORE-V) Xcvmac instructions. */
{"cv.mac", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MAC, MASK_CV_MAC, match_opcode, 0},
{"cv.msu", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MSU, MASK_CV_MSU, match_opcode, 0},
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