[binutils-gdb] RISC-V: Support Zalasr extension.
Jeff Law
law@sourceware.org
Mon Jun 22 14:22:39 GMT 2026
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=db7f7dd31576bc2e5c004aa4484fe75265cc1ea2
commit db7f7dd31576bc2e5c004aa4484fe75265cc1ea2
Author: Jiawei <jiawei@iscas.ac.cn>
Date: Mon Jun 22 08:13:44 2026 -0600
RISC-V: Support Zalasr extension.
This patch supports Zalasr extension(load-acquire/store-release) instructions.
https://github.com/riscv/riscv-zalasr
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): New ext.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* NEWS: Support Zalasr extension.
* testsuite/gas/riscv/march-help.l: New ext.
* testsuite/gas/riscv/zalasr.d: New test.
* testsuite/gas/riscv/zalasr.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_LBA): New match opcode.
(MASK_LBA): New mask opcode.
(MATCH_LHA): New match opcode.
(MASK_LHA): New mask opcode.
(MATCH_LWA): New match opcode.
(MASK_LWA): New mask opcode.
(MATCH_LDA): New match opcode.
(MASK_LDA): New mask opcode.
(MATCH_SBR): New match opcode.
(MASK_SBR): New mask opcode.
(MATCH_SHR): New match opcode.
(MASK_SHR): New mask opcode.
(MATCH_SWR): New match opcode.
(MASK_SWR): New mask opcode.
(MATCH_SDR): New match opcode.
(MASK_SDR): New mask opcode.
(DECLARE_INSN): New insn declare.
* opcode/riscv.h (enum riscv_insn_class): New ext.
opcodes/ChangeLog:
* riscv-opc.c: New instructions def.
Diff:
---
bfd/elfxx-riscv.c | 6 ++++++
gas/NEWS | 3 +++
gas/testsuite/gas/riscv/march-help.l | 1 +
gas/testsuite/gas/riscv/zalasr.d | 26 ++++++++++++++++++++++++++
gas/testsuite/gas/riscv/zalasr.s | 17 +++++++++++++++++
include/opcode/riscv-opc.h | 26 ++++++++++++++++++++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 18 ++++++++++++++++++
8 files changed, 98 insertions(+)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 67fbf0f72ca..3057eee752c 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1220,6 +1220,7 @@ static const struct riscv_implicit_subset riscv_implicit_subsets[] =
{"zabha", "+zaamo", check_implicit_always},
{"zacas", "+zaamo", check_implicit_always},
{"a", "+zaamo,+zalrsc", check_implicit_always},
+ {"zalasr", "+zaamo,+zalrsc,+zabha", check_implicit_always},
{"xsfvcp", "+zve32x", check_implicit_always},
{"xsfvqmaccqoq", "+zve32x,+zvl256b", check_implicit_always},
@@ -1478,6 +1479,7 @@ static const struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zaamo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zabha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zacas", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zalasr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zalrsc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zfbfmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2860,6 +2862,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
case INSN_CLASS_ZABHA_AND_ZACAS:
return (riscv_subset_supports (rps, "zabha")
&& riscv_subset_supports (rps, "zacas"));
+ case INSN_CLASS_ZALASR:
+ return riscv_subset_supports (rps, "zalasr");
case INSN_CLASS_ZALRSC:
return riscv_subset_supports (rps, "zalrsc");
case INSN_CLASS_ZAWRS:
@@ -3155,6 +3159,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return "zabha";
}
return "zacas";
+ case INSN_CLASS_ZALASR:
+ return "zalasr";
case INSN_CLASS_ZALRSC:
return "zalrsc";
case INSN_CLASS_ZAWRS:
diff --git a/gas/NEWS b/gas/NEWS
index bfb42063575..ca5a4c22ed7 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -5,6 +5,9 @@
ABI was adopted) are now considered obsolete. They are now deprecated
and will be removed in a future release.
+* Add support for RISC-V standard extensions:
+ zalasr v1.0
+
Changes in 2.46:
* Add support for AMD Zen6 processor.
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index 0ce2f896735..812c4277aed 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -35,6 +35,7 @@ All available -march extensions for RISC-V:
zaamo 1.0
zabha 1.0
zacas 1.0
+ zalasr 1.0
zalrsc 1.0
zawrs 1.0
zfbfmin 1.0
diff --git a/gas/testsuite/gas/riscv/zalasr.d b/gas/testsuite/gas/riscv/zalasr.d
new file mode 100644
index 00000000000..f920d779740
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zalasr.d
@@ -0,0 +1,26 @@
+#as: -march=rv64i_zalasr
+#source: zalasr.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+3405052f[ ]+lb.aq[ ]+a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+3605052f[ ]+lb.aqrl[ ]+a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+3405152f[ ]+lh.aq[ ]+a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+3605152f[ ]+lh.aqrl[ ]+a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+3405252f[ ]+lw.aq[ ]+a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+3605252f[ ]+lw.aqrl[ ]+a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+3405352f[ ]+ld.aq[ ]+a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+3605352f[ ]+ld.aqrl[ ]+a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+3aa5002f[ ]+sb.rl[ ]+a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+3ea5002f[ ]+sb.aqrl[ ]+a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+3aa5102f[ ]+sh.rl[ ]+a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+3ea5102f[ ]+sh.aqrl[ ]+a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+3aa5202f[ ]+sw.rl[ ]+a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+3ea5202f[ ]+sw.aqrl[ ]+a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+3aa5302f[ ]+sd.rl[ ]+a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+3ea5302f[ ]+sd.aqrl[ ]+a0,\(a0\)
diff --git a/gas/testsuite/gas/riscv/zalasr.s b/gas/testsuite/gas/riscv/zalasr.s
new file mode 100644
index 00000000000..875798f46a0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zalasr.s
@@ -0,0 +1,17 @@
+target:
+ lb.aq a0, 0(a0)
+ lb.aqrl a0, 0(a0)
+ lh.aq a0, 0(a0)
+ lh.aqrl a0, 0(a0)
+ lw.aq a0, 0(a0)
+ lw.aqrl a0, 0(a0)
+ ld.aq a0, 0(a0)
+ ld.aqrl a0, 0(a0)
+ sb.rl a0, 0(a0)
+ sb.aqrl a0, 0(a0)
+ sh.rl a0, 0(a0)
+ sh.aqrl a0, 0(a0)
+ sw.rl a0, 0(a0)
+ sw.aqrl a0, 0(a0)
+ sd.rl a0, 0(a0)
+ sd.aqrl a0, 0(a0)
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 6f2775c6152..184e5356dc9 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2529,6 +2529,23 @@
#define MASK_AMOCAS_D 0xf800707f
#define MATCH_AMOCAS_Q 0x2800402f
#define MASK_AMOCAS_Q 0xf800707f
+/* Zalasr instructions. */
+#define MATCH_LBA 0x3000002f
+#define MASK_LBA 0xf9f0707f
+#define MATCH_LHA 0x3000102f
+#define MASK_LHA 0xf9f0707f
+#define MATCH_LWA 0x3000202f
+#define MASK_LWA 0xf9f0707f
+#define MATCH_LDA 0x3000302f
+#define MASK_LDA 0xf9f0707f
+#define MATCH_SBR 0x3800002f
+#define MASK_SBR 0xf8007fff
+#define MATCH_SHR 0x3800102f
+#define MASK_SHR 0xf8007fff
+#define MATCH_SWR 0x3800202f
+#define MASK_SWR 0xf8007fff
+#define MATCH_SDR 0x3800302f
+#define MASK_SDR 0xf8007fff
/* Zawrs instructions. */
#define MATCH_WRS_NTO 0x00d00073
#define MASK_WRS_NTO 0xffffffff
@@ -4876,6 +4893,15 @@ DECLARE_INSN(cm_mva01s, MATCH_CM_MVA01S, MASK_CM_MVA01S)
/* Zcmt instructions. */
DECLARE_INSN(cm_jt, MATCH_CM_JT, MASK_CM_JT)
DECLARE_INSN(cm_jalt, MATCH_CM_JALT, MASK_CM_JALT)
+/* Zalasr instructions. */
+DECLARE_INSN(lb_aq, MATCH_LBA, MASK_LBA)
+DECLARE_INSN(lh_aq, MATCH_LHA, MASK_LHA)
+DECLARE_INSN(lw_aq, MATCH_LWA, MASK_LWA)
+DECLARE_INSN(ld_aq, MATCH_LDA, MASK_LDA)
+DECLARE_INSN(sb_rl, MATCH_SBR, MASK_SBR)
+DECLARE_INSN(sh_rl, MATCH_SHR, MASK_SHR)
+DECLARE_INSN(sw_rl, MATCH_SWR, MASK_SWR)
+DECLARE_INSN(sd_rl, MATCH_SDR, MASK_SDR)
/* Smctr/Ssctr instruction. */
DECLARE_INSN(sctrclr, MATCH_SCTRCLR, MASK_SCTRCLR)
/* Smrnmi instruction */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index de105f5df8b..cd276aa62f2 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -509,6 +509,7 @@ enum riscv_insn_class
INSN_CLASS_ZIMOP,
INSN_CLASS_ZMMUL,
INSN_CLASS_ZAAMO,
+ INSN_CLASS_ZALASR,
INSN_CLASS_ZALRSC,
INSN_CLASS_ZAWRS,
INSN_CLASS_F_INX,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index ba155335878..22a6e72b5b0 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -886,6 +886,24 @@ const struct riscv_opcode riscv_opcodes[] =
{"amocas.d.aqrl", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_D|MASK_AQRL, MASK_AMOCAS_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
{"amocas.q.aqrl", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_Q|MASK_AQRL, MASK_AMOCAS_Q|MASK_AQRL, match_rs2_rd_even, INSN_DREF|INSN_16_BYTE },
+/* Zalasr instruction subset. */
+{"lb.aq", 0, INSN_CLASS_ZALASR, "d,0(s)", MATCH_LBA|MASK_AQ, MASK_LBA|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE },
+{"lb.aqrl", 0, INSN_CLASS_ZALASR, "d,0(s)", MATCH_LBA|MASK_AQRL, MASK_LBA|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE },
+{"lh.aq", 0, INSN_CLASS_ZALASR, "d,0(s)", MATCH_LHA|MASK_AQ, MASK_LHA|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
+{"lh.aqrl", 0, INSN_CLASS_ZALASR, "d,0(s)", MATCH_LHA|MASK_AQRL, MASK_LHA|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
+{"lw.aq", 0, INSN_CLASS_ZALASR, "d,0(s)", MATCH_LWA|MASK_AQ, MASK_LWA|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"lw.aqrl", 0, INSN_CLASS_ZALASR, "d,0(s)", MATCH_LWA|MASK_AQRL, MASK_LWA|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"ld.aq", 64, INSN_CLASS_ZALASR, "d,0(s)", MATCH_LDA|MASK_AQ, MASK_LDA|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"ld.aqrl", 64, INSN_CLASS_ZALASR, "d,0(s)", MATCH_LDA|MASK_AQRL, MASK_LDA|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"sb.rl", 0, INSN_CLASS_ZALASR, "t,0(s)", MATCH_SBR|MASK_RL, MASK_SBR|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE },
+{"sb.aqrl", 0, INSN_CLASS_ZALASR, "t,0(s)", MATCH_SBR|MASK_AQRL, MASK_SBR|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE },
+{"sh.rl", 0, INSN_CLASS_ZALASR, "t,0(s)", MATCH_SHR|MASK_RL, MASK_SHR|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
+{"sh.aqrl", 0, INSN_CLASS_ZALASR, "t,0(s)", MATCH_SHR|MASK_AQRL, MASK_SHR|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
+{"sw.rl", 0, INSN_CLASS_ZALASR, "t,0(s)", MATCH_SWR|MASK_RL, MASK_SWR|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"sw.aqrl", 0, INSN_CLASS_ZALASR, "t,0(s)", MATCH_SWR|MASK_AQRL, MASK_SWR|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"sd.rl", 64, INSN_CLASS_ZALASR, "t,0(s)", MATCH_SDR|MASK_RL, MASK_SDR|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"sd.aqrl", 64, INSN_CLASS_ZALASR, "t,0(s)", MATCH_SDR|MASK_AQRL, MASK_SDR|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
+
/* Multiply/Divide instruction subset. */
{"mul", 0, INSN_CLASS_ZCB_AND_ZMMUL, "Cs,Cw,Ct", MATCH_C_MUL, MASK_C_MUL, match_opcode, INSN_ALIAS },
{"mul", 0, INSN_CLASS_ZMMUL, "d,s,t", MATCH_MUL, MASK_MUL, match_opcode, 0 },
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