[binutils-gdb/binutils-2_47-branch] This is the 2.47 release
Nick Clifton
nickc@sourceware.org
Sun Jul 26 07:48:34 GMT 2026
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=6ce87bbc521cf46eaee9a1f7ef61cee2cdfb3e32
commit 6ce87bbc521cf46eaee9a1f7ef61cee2cdfb3e32
Author: Nick Clifton <nickc@redhat.com>
Date: Sun Jul 26 08:48:22 2026 +0100
This is the 2.47 release
Diff:
---
ChangeLog.git | 351452 ++++++++++++++++++++++++++++++++++++++
bfd/configure | 20 +-
bfd/version.m4 | 2 +-
binutils/configure | 20 +-
gas/configure | 20 +-
gdb/aclocal.m4 | 16 +-
gprof/configure | 20 +-
gprofng/configure | 20 +-
gprofng/doc/version.texi | 4 +-
gprofng/libcollector/configure | 20 +-
ld/configure | 20 +-
libdecnumber/aclocal.m4 | 4 +-
libiberty/functions.texi | 70 +-
opcodes/configure | 20 +-
src-release.sh | 2 +-
15 files changed, 351593 insertions(+), 117 deletions(-)
diff --git a/ChangeLog.git b/ChangeLog.git
new file mode 100644
index 00000000000..e50142aab4e
--- /dev/null
+++ b/ChangeLog.git
@@ -0,0 +1,351452 @@
+2026-07-26 Nick Clifton <nickc@redhat.com>
+
+ Updated translations
+
+2026-07-26 Jan Beulich <jbeulich@suse.com>
+
+ Commit 0e89ce812b79 ("aarch64: Remove cast from struct initializer") didn't go quite far enough: The building of aarch64-gen itself has a similar issue. Cover that as well. Since FLD_CONST_* are used only there, move their #define-s there rather than introducing more #undef-s.
+
+2026-07-26 GDB Administrator <gdbadmin@sourceware.org>
+
+ Automatic date update in version.in
+
+2026-07-25 GDB Administrator <gdbadmin@sourceware.org>
+
+ Automatic date update in version.in
+
+2026-07-24 GDB Administrator <gdbadmin@sourceware.org>
+
+ Automatic date update in version.in
+
+2026-07-23 GDB Administrator <gdbadmin@sourceware.org>
+
+ Automatic date update in version.in
+
+2026-07-22 GDB Administrator <gdbadmin@sourceware.org>
+
+ Automatic date update in version.in
+
+2026-07-21 GDB Administrator <gdbadmin@sourceware.org>
+
+ Automatic date update in version.in
+
+2026-07-20 GDB Administrator <gdbadmin@sourceware.org>
+
+ Automatic date update in version.in
+
+2026-07-19 GDB Administrator <gdbadmin@sourceware.org>
+
+ Automatic date update in version.in
+
+2026-07-17 Alan Modra <amodra@gmail.com>
+
+ loongarch gcc-4.9 build error
+ gas/config/tc-loongarch.c: In function ‘md_apply_fix’:
+ gas/config/tc-loongarch.c:1886:7: error: a label can only be part of a statement and a declaration is not a statement
+ unsigned int subtype;
+ ^
+
+ * config/tc-loongarch.c (md_apply_fix <BFD_RELOC_LARCH_CFA>):
+ Avoid gcc-4.9 error.
+
+ (cherry picked from commit d36b7ef85a30cda5ea19110920f61727be2fd984)
+
+2026-07-16 Xi Ruoyao <xry111@xry111.site>
+
+ [v2] LoongArch: only insert align section for ld -r if an input has R_LARCH_ALIGN or R_LARCH_RELAX
+ Commit 8bf4b69718d4 ("LoongArch: Fix relaxation alignment with ld -r (PR 33236)") has broken the kernel modules on Debian sid.
+ The expectation of the kernel is all the source files which would be linked into a module are compiled with -mno-relax so the
+ module should not contain R_LARCH_ALIGN, thus the module loader rejects any module containing R_LARCH_ALIGN. To restore the
+ correctness of the expectation, only insert the align section if an input has R_LARCH_ALIGN or R_LARCH_ALIGN (i.e. bytes may
+ be removed from that input). Regardless of the kernel modules, it also does not make too much sense to bloat the output with
+ NOPs and R_LARCH_ALIGN if no input ever contains R_LARCH_ALIGN and R_LARCH_ALIGN anyway.
+
+2026-07-15 Alan Modra <amodra@gmail.com>
+
+ readelf.c gcc-4.9 compile error
+ gcc-4.9 doesn't like an empty initialiser.
+
+ binutils/readelf.c: In function ‘process_relocs’:
+ binutils/readelf.c:10229:5: error: missing initializer for field ‘sh_name’ of ‘Elf_Internal_Shdr’ [-Werror=missing-field-initializers]
+ Elf_Internal_Shdr section = {};
+
+ * readelf.c (process_relocs): Avoid gcc-4.9 compile error.
+
+ (cherry picked from commit 4643afba9100939b16f50e13f085fc5bd0284930)
+
+2026-07-15 Alan Modra <amodra@gmail.com>
+
+ arm: remove stray backslash in warning message
+ Fixes an error introduced in 2004 by commit d003868ea7bf.
+
+ (cherry picked from commit 4d5b46e3e3dccaa23ca904e65dda3729cf4219d9)
+
+2026-07-15 Alan Modra <amodra@gmail.com>
+
+ Re: readelf: Save and dump the original section header values
+ This is a modified version of the mainline patch without fixes for
+ warning messages, so that translations do not need to be updated.
+
+ I decided it wasn't worth reporting specifics about
+ a malloc failure when allocating a relatively small fixed size buffer.
+ It would be different if some large chunk of file data caused a malloc
+ fail.
+
+ The patch also fixes a potential orig_section_headers buffer overflow,
+ caused by allocating a single element array when probing, hitting some
+ early error in process_file_header, then attempting to access it as an
+ array of e_shnum entries in free_filedata.
+
+ * readelf.c (save_original_section_header_values): Use xmalloc
+ rather than reporting a more specific error. Drop now unused
+ function parameters.
+ (validate_section_info): Delete "dynamic" and "probe" params.
+ Don't save orig header for fake section header passing relr
+ dynamic tags. Avoid possible arithmetic overflow when
+ checking sh_size.
+ (get_32bit_section_headers): Don't allocate orig_section_headers
+ or call validate_section_info when probing.
+ (get_64bit_section_headers): Likewise.
+ (process_relocs): Update validate_section_info call when
+ handling relr.
+
+ (cherry picked from commit e7c25d560b0ee365a80dc953285f8e84f622f0b5)
+
+2026-07-15 Alice Carlotti <alice.carlotti@arm.com>
+
+ aarch64: Remove cast from struct initializer
+ This fixes the error reported when compiling with GCC 4.9:
+
+ opcodes/aarch64-opc-2.c:29:3: error: initializer element is not constant
+ {AARCH64_OPND_CLASS_INT_REG, "Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "an integer register"},
+ ^
+ opcodes/aarch64-opc-2.c:29:3: error: (near initialization for ‘aarch64_operands[1].fields[0]’)
+
+2026-07-13 H.J. Lu <hjl.tools@gmail.com>
+
+ x86: Disable XCHG to MOV optimization
+ The -O option was added to x86 assembler by
+
+ commit b6f8c7c45229a8a5405079e586bfbaad396d2cbe
+ Author: H.J. Lu <hjl.tools@gmail.com>
+ Date: Tue Feb 27 07:36:33 2018 -0800
+
+ x86: Add -O[2|s] assembler command-line options
+
+ On x86, some instructions have alternate shorter encodings:
+
+ 1. When the upper 32 bits of destination registers of
+
+ andq $imm31, %r64
+ testq $imm31, %r64
+ xorq %r64, %r64
+ subq %r64, %r64
+
+ known to be zero, we can encode them without the REX_W bit:
+
+ andl $imm31, %r32
+ testl $imm31, %r32
+ xorl %r32, %r32
+ subl %r32, %r32
+
+ This optimization is enabled with -O, -O2 and -Os.
+ 2. Since 0xb0 mov with 32-bit destination registers zero-extends 32-bit
+ immediate to 64-bit destination register, we can use it to encode 64-bit
+ mov with 32-bit immediates. This optimization is enabled with -O, -O2
+ and -Os.
+ 3. Since the upper bits of destination registers of VEX128 and EVEX128
+ instructions are extended to zero, if all bits of destination registers
+ of AVX256 or AVX512 instructions are zero, we can use VEX128 or EVEX128
+ encoding to encode AVX256 or AVX512 instructions. When 2 source
+ registers are identical, AVX256 and AVX512 andn and xor instructions:
+
+ VOP %reg, %reg, %dest_reg
+
+ can be encoded with
+
+ VOP128 %reg, %reg, %dest_reg
+
+ This optimization is enabled with -O2 and -Os.
+ 4. 16-bit, 32-bit and 64-bit register tests with immediate may be
+ encoded as 8-bit register test with immediate. This optimization is
+ enabled with -Os.
+
+ These optimizations were intended for compiler generated assembly codes.
+ The optimization changes may take a long time to be put into GCC. The
+ similar SSE move encoding optimization for GCC was first proposed in
+ Feb, 2019:
+
+ https://gcc.gnu.org/pipermail/gcc-patches/2019-February/516941.html
+
+ It finally went in Mar, 2020:
+
+ commit 5358e8f5800daa0012fc9d06705d64bbb21fa07b
+ Author: H.J. Lu <hjl.tools@gmail.com>
+ Date: Thu Mar 5 16:45:05 2020 -0800
+
+ i386: Properly encode vector registers in vector move
+
+ Such optimizations are useful for compiler generated codes since they
+ work with released versions of GCC which don't have such optimized
+ encoding. We assume that it is safe to use on compiler generated codes.
+ When we are informed that an assembler optimization introduces a
+ significant drawback, we will investigate its drawbacks and benefits.
+ If its drawbacks outweigh its benefits, such optimization should be
+ removed.
+
+ commit 1c3c3e4b3c2ac2eed9abcbce0b9cba1be10ed3f0
+ Author: Jan Beulich <jbeulich@suse.com>
+ Date: Fri Jun 19 09:47:21 2026 +0200
+
+ x86: optimize XCHG to MOV for same-register forms
+
+ breaks valgrind:
+
+ https://bugs.kde.org/show_bug.cgi?id=522533
+
+ "xchgl %ecx,%ecx" in VALGRIND_GET_NR_CONTEXT, which is defined in
+ /usr/include/valgrind/valgrind.h:
+
+ #define VALGRIND_GET_NR_CONTEXT(_zzq_rlval) \
+ { volatile OrigFn* _zzq_orig = &(_zzq_rlval); \
+ volatile unsigned int __addr; \
+ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
+ /* %EAX = guest_NRADDR */ \
+ "xchgl %%ecx,%%ecx" \
+ : "=a" (__addr) \
+ : \
+ : "cc", "memory" \
+ ); \
+ _zzq_orig->nraddr = __addr; \
+ }
+
+ has special meanings and shouldn't be changed by assembler even when
+ assembler optimization is enabled. Since there are no any evidences
+ to show its benefits, we can't say that it is useful at all. This
+ patch disables this optimization, which may be enabled with a different
+ option.
+
+ gas/
+
+ PR gas/34343
+ * config/tc-i386.c (optimize_for_disabled_optimizations): New.
+ (optimize_encoding): Optimize "xchg %rN, %rN" to "mov %rN, %rN"
+ only if optimize_for_disabled_optimizations isn't 0.
+ * testsuite/gas/i386/optimize-2b.d: Updated.
+ * testsuite/gas/i386/x86-64-optimize-3b.d: Likewise.
+
+ (cherry picked from commit 49652cd8ecbb4c305a9a0e9099016edb138e6953)
+
+2026-07-12 Alan Modra <amodra@gmail.com>
+
+ Re: bfd/ELF: fold BFD_RELOC_<arch>_GOTOFF*
+ Commit 705b90feb82c missed updating some frv and lm32 source files,
+ resulting in build breakage if generated files in opcodes/ are
+ regenerated.
+
+ (cherry picked from commit fb66599b4d0b97fc14242f3c7a6f04a5821ca36a)
+
+2026-07-12 Nick Clifton <nickc@redhat.com>
+
+ Set version to 2.46.90 and regenerate files
+
+ Add markers to NEWS files for 2.47 release
+
+2026-07-12 GDB Administrator <gdbadmin@sourceware.org>
+
+ Automatic date update in version.in
+
+2026-07-11 Jan Dubiec <jdx@o2.pl>
+
+ H8: Set H8/300H as the default architecture for the H8 family.
+ H8/300H uses 32-bit addresses in its default advanced mode, whereas
+ H8/300 uses 16-bit addresses. Updates affected test cases accordingly.
+
+ bfd/
+ * cpu-h8300.c: Set H8/300H as the default architecture
+ for the H8 family.
+ gas/
+ * config/tc-h8300.c: Set H8/300H as the default architecture
+ for the H8 family.
+ * NEWS: Add info about the above change.
+ ld/
+ * configure.tgt: Set H8/300H as the default architecture
+ for the H8 family.
+ * NEWS: Add info about the above change.
+ * testsuite/ld-elf/elf.exp: Expect 32-bit addresses/pointers
+ for H8 on __patchable_function_entries tests.
+
+2026-07-11 Alan Modra <amodra@gmail.com>
+
+ aarch64-pe fails of tls-debug tests
+ These fail to assemble since they use ELF section directives. There
+ isn't any need to test for an aarch64 target since that is done in
+ aarch64.exp.
+
+ * testsuite/gas/aarch64/tls-debug.d: Replace aarch64 target test
+ with is_elf_format.
+ * testsuite/gas/aarch64/tls-debug-bad.d: Likewise.
+
+2026-07-11 Matthieu Longo <matthieu.longo@arm.com>
+
+ gdb/linux-tdep: change linux_fill_prpsinfo to return bool
+ Change linux_fill_prpsinfo() to return a boolean instead of an integer, since
+ it only reports success or failure.
+ Replace the returned integer values 1 and 0 with true and false respectively.
+
+ Reviewed-by: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
+ Approved-By: Simon Marchi <simon.marchi@efficios.com>
+
+2026-07-11 GDB Administrator <gdbadmin@sourceware.org>
+
+ Automatic date update in version.in
+
+2026-07-10 Pedro Alves <pedro@palves.net>
+
+ gdb.base/execl-update-breakpoints.exp: Don't execl forever
+ execl-update-breakpoints.c is compiled as both
+ execl-update-breakpoints1 and execl-update-breakpoints2.
+
+ execl-update-breakpoints1 checks to see if the last character in its
+ filename is '1', and if so, replace it with '2' and execl the result.
+
+ On Windows, this fails to take into account that the filename may have
+ an ".exe" extension. The result is that the execl-update-breakpoints1
+ executable execs itself forever.
+
+ This patch fixes it by taking the .exe extension into account.
+
+ (Note that neither native Windows nor Cygwin support following execs,
+ and maybe the testcase will eventually be skipped there, but even
+ then, if someone enables follow-exec testing there, we'd want it to
+ handle the .exe extension, so I think it's better to adjust the
+ testcase than not.)
+
+ Now, on e.g. GNU/Linux, if you run execl-update-breakpoints1 manually,
+ you'll see that it also execs forever, but this time, what happens is
+ that execl-update-breakpoints1 execs execl-update-breakpoints2, and
+ then it's execl-update-breakpoints2 that execs itself forever. There
+ is no reason for execl-update-breakpoints2 to exec. It's just that
+ the testcase is assuming that the process is killed when the testcase
+ is over. It's just cleaner if execl-update-breakpoints1 execs
+ execl-update-breakpoints2, and then execl-update-breakpoints2 just
+ cleanly exits. The patch does that too.
+
+ And then, the test program should really be erroring out if neither
+ '1' nor '2' is found at the tail of the executable. Done too.
+
+ Approved-By: Simon Marchi <simon.marchi@efficios.com>
+ Change-Id: Id88830cd8dff2c63dd69b827d4ba79743aa9ebca
+
+2026-07-10 Alice Carlotti <alice.carlotti@arm.com>
+
+ aarch64: Update FEAT_TPS and FEAT_TPSP system registers
+ The specification has been changed to use individual tpcr* registers,
+ instead of the original tpmin*/tpmax* pairs.
+
+2026-07-10 Alice Carlotti <alice.carlotti@arm.com>
+
+ aarch64: Add support for FEAT_SME_FA64
+ Add "+sme-f64" to the list of architecture extensions. This has already
+ been supported in LLVM for several years.
+
+ We don't need to update the feature requirements for any opcodes,
+ because FEAT_SME_FA64 only enables instructions that were already
+ available in non-streaming mode, and the feature checks don't know what
+ mode an instruction will be run under.
+
+2026-07-10 Alice Carlotti <alice.carlotti@arm.com>
+
+ aarch64 doc: Fix description of .unreq directive.
+
+ aarch64: Fix .unreq of predefined aliases
+ Attempting to free a static reg_entry is invalid, so use
+ insert_reg_alias to create a dynamic copy of the content.
+
+ aarch64: Drop "" from hint option hash table
+ An empty string is the only option where the upper and lower case forms
+ are identical, so this allows the upper case insertion logic to be
+ simplified as well.
+
+ aarch64: Replace FLD_* macros in do_misc_{en|de}coding
+ Replace the macros with explicit AARCH64_FIELD calls, and extend the
+ comments to clarify which aliased instructions are involved.
+
+2026-07-10 Alice Carlotti <alice.carlotti@arm.com>
+
+ aarch64: Remove disassembly restriction on OP_MOV_Z_Zi
+ Disassembly for the OP_MOV_Z_Zi opcode artificially rejected a zero
+ index value, to indicate that the preferred disassembly uses a different
+ alias. This is more naturally indicated by specifying the other alias
+ as a higher priority.
+
+ Update the alias priority, and remove the zero check and the now-unused
+ OP_MOV_Z_Zi enum value.
+
+2026-07-10 Alice Carlotti <alice.carlotti@arm.com>
+
+ aarch64: Inline all FLD_* uses in aarch64-tbl.h
+ Inline all non-constant field definitions into operand field lists, and
+ remove the resulting unused FLD_* macros. For brevity, define FLD as an
+ alias for AARCH64_FLD in aarch64-gen.c.
+
+ aarch64: Write AARCH64_FIELD calls to aarch64-opc-2.c
+ Parse the operand field lists in aarch64-gen.c, and rewrite the content
+ to aarch64-opc-2.c using AARCH64_FIELD calls. This allows aarch64-tbl.h
+ to use shorthand macros without exporting them elsewhere.
+
+2026-07-10 Alice Carlotti <alice.carlotti@arm.com>
+
+ aarch64: Remove aarch64_field_kind indirection
+ Replace all uses of the aarch64_field_kind enum with direct uses of an
+ aarch64_field struct instead. Add macro defines mapping the old enum
+ names to their corresponding aarch64_field values, to reduce the initial
+ diff. These can be substituted directly into their uses in subsequent
+ patches.
+
+ Once the macro defines are replaced, this should make it simpler to read
+ the code, because it will no longer be necessary to look in a separate
+ table to find out which opcode bits a field actually uses. This has
+ been a growing problem over the years - originally there was a simpler
+ correspondence between field names and positions, but as the
+ architecture has grown it has become harder to guess a field's position
+ from it's name alone.
+
+2026-07-10 mengqinggang <mengqinggang@loongson.cn>
+
+ LoongArch: Support R_LARCH_TLS_DTPREL32/64 used in debug section
+ Simplify R_LARCH_TLS_DTPREL32/64 relocations processing.
+ Return the offset to TLS block for symbol.
+
+ Change R_LARCH_TLS_DTPREL32/64 partial_inplace to false since
+ LoongArch uses RELA relocations.
+
+2026-07-10 mengqinggang <mengqinggang@loongson.cn>
+
+ LoongArch: Emit alignment relocations after relaxed instructions
+ Alignment cannot change before relaxed instructions.
+ Emit alignment relocations only after them.
+
+ Similar with https://github.com/llvm/llvm-project/pull/150816.
+
+2026-07-10 mengqinggang <mengqinggang@loongson.cn>
+
+ LoongArch: Emit fewer relocations for label subtraction
+ Mark the frag and section to indicate if they have a relaxed instruction.
+
+ For label subtraction, if there are no relaxed instructions between addsy
+ and subsy, do not emit relocations.
+
+2026-07-10 mengqinggang <mengqinggang@loongson.cn>
+
+ LoongArch: Do not emit relocation if addsy and subsy are in the same frag
+ Let relaxed instructions and alignment nops in a single frag.
+ Do not emit relocation if addsy and subsy are in the same frag.
+
+ LoongArch: Fix the size of tls desc relocations
+ Change the size of R_LARCH_TLS_DESC64_* from 8 to 4.
+
+2026-07-10 GDB Administrator <gdbadmin@sourceware.org>
+
+ Automatic date update in version.in
+
+2026-07-09 Pedro Alves <pedro@palves.net>
+
+ gdb/hip: Prepare for DWARF-assembler-based HIP testcases
+ Compiling a testcase with debug info (by passing passing "debug" as
+ gdb_compile option) has the effect of passing -g to the compiler. -g
+ in turn enables an LLVM option that is essential for debugging:
+ '-mllvm -amdgpu-spill-cfi-saved-regs'.
+
+ That option affects code generation, and some features of the DWARF
+ assembler machinery rely on code generated by the compiler without -g
+ to be the exact same as the code generated with -g.
+
+ This patch addresses that by always compiling with the LLVM option
+ that -g would enable.
+
+ Approved-by: Lancelot Six <lancelot.six@amd.com> (amdgpu)
+ Change-Id: I64a938edf97c85d0ea9fc34b37071daa560de7e7
+
+2026-07-09 Nick Alcock <nix@esperi.org.uk>
+
+ MAINTAINERS: update my email address
+
+2026-07-09 Georg-Johann Lay <avr@gjlay.de>
+
+ AVR: Fix typo / white space in include/opcode/avr.h
+ include/
+ * opcode/avr.h: Fix typo in comment + trailing space.
+
+2026-07-09 H.J. Lu <hjl.tools@gmail.com>
+
+ readelf: Save and dump the original section header values
+ validate_section_info clears the garbage values in the section header
+ to avoid crash later. Save and dump the original section header values
+ to make the garbage values in the section header visible when dumping
+ section headers.
+
+ Note: orig_section_headers, instead of sane_section_headers, is added to
+ filedata since filedata->section_headers is used in many places. Replace
+ filedata->section_headers with filedata->sane_section_headers requires
+ a much bigger change.
+
+ * readelf.c (filedata): Add orig_section_headers.
+ (save_original_section_header_values): New.
+ (validate_section_info): Add a pointer to the original section
+ header and call save_original_section_header_values to save the
+ original section header values before clearing the section header
+ fields.
+ (get_32bit_section_headers): Allocate the original section header
+ buffer. Pass the original section header pointer to
+ validate_section_info.
+ (get_64bit_section_headers): Likewise.
+ (process_section_headers): Dump the original section header
+ values if they exist.
+ (process_relocs): Pass a dummy original section pointer to
+ validate_section_info.
+ (free_filedata): Free filedata->orig_section_headers.
+ * testsuite/binutils-all/corrupt-1.elf.bz2: New file.
+ * testsuite/binutils-all/corrupt-1.r: Likewise.
+ * testsuite/binutils-all/readelf.exp: Run corrupt-1.elf test.
+
+2026-07-09 Ronald Hecht <ronald.hecht@gmx.de>
+
+ gdb: z80: Fix endless loop in frame unwinder and validate saved register types
+ In z80_frame_unwind_cache, the loop scanning for the frame base pointer
+ (for (;; ++sp)) could run into an endless loop or scan too far if the
+ termination condition (sp < this_base) was not met due to corrupted
+ or unexpected stack layouts. This patch introduces a loop_count to
+ limit the scan to a maximum of 2 * addr_len iterations.
+
+ Additionally, when iterating through saved registers to adjust their
+ offsets into concrete addresses, the code now explicitly checks if
+ the register actually holds an address using is_addr() before calling
+ addr(). This prevents potential assertions or undefined behavior for
+ registers that do not contain valid address data.
+
+ gdb/ChangeLog:
+
+ * z80-tdep.c (z80_frame_unwind_cache): Limit stack scanning
+ to 2 * addr_len iterations to prevent endless loops. Check
+ is_addr() before adjusting saved register addresses.
+
+ Approved-By: Kevin Buettner <kevinb@redhat.com>
+
+2026-07-09 Nelson Chu <nelson.chu@sifive.com>
+
+ RISC-V: Minor cleanup for opcodes/riscv-opc.c
+ Unify vendor extension comments.
+
+2026-07-09 Ethan Y. C. Liang <ycl669@andestech.com>
+
+ RISC-V: Check for conflicting extensions when the linker merges arch attributes
+ The linker validates the arch of each input when parsing it, but never
+ checks the merged arch as a whole, so conflicting extensions could
+ silently slip through. The merge can even imply extensions that
+ neither input implies alone, e.g. `c' from one input and `d' from
+ another imply `zcd', which conflicts with `zcmp'.
+
+ After merging the input archs, add the implicit extensions to the
+ merged arch, then run the conflict checks on it and reject the merge
+ if any conflict is found. Add tests for such merges.
+
+2026-07-09 Ethan Y. C. Liang <ycl669@andestech.com>
+
+ RISC-V: Release subset lists on all paths when the linker merges arch attributes
+ riscv_merge_arch_attr_info returned early on the error paths without
+ releasing in_subsets, out_subsets and merged_subsets, so the nodes
+ already added to them were leaked. The leaked nodes of in_subsets
+ and out_subsets also carry over into the next merge.
+
+ Route every post-parse error path through a single cleanup exit that
+ releases all three subset lists, and drop the now-redundant reset of
+ merged_subsets at entry.
+
+2026-07-09 Nelson Chu <nelson.chu@sifive.com>
+
+ RISC-V: Minor cleanup for include/opcode/riscv-opc.h and vendor gas testcases
+ For include/opcode/riscv-opc.h, reorder zicfiss and zicfilp stuff, and unify
+ vendor extension comments. For gas tescases, unify vendor testcase names.
+
+2026-07-09 GDB Administrator <gdbadmin@sourceware.org>
+
+ Automatic date update in version.in
+
+2026-07-08 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
+
+ aarch64: Fix %dtprel relocations size.
+ The AArch64 ELF ABI [1] requires DTPREL relocations to be
+ 8 bytes wide, so added a check to reject %dtprel when used
+ with anything other than .xword.
+
+ [1] https://github.com/ARM-software/abi-aa/blob/main/aaelf64/aaelf64.rst#5715dynamic-relocations
+
+2026-07-08 Tankut Baris Aktemur <tankutbaris.aktemur@amd.com>
+
+ gdb, amd-dbgapi-target: fix extra space in wave_coordinates
+ In commit 57f5450 ("gdb, amd-dbgapi-target: split
+ wave_coordinates::to_string"), I mistakenly left extra space in the
+ output of wave_coordinates' string methods. Fix this.
+
+ Approved-by: Lancelot Six <lancelot.six@amd.com> (amdgpu)
+
+2026-07-08 Andrew Burgess <aburgess@redhat.com>
+
+ gdb/python: remove frame_object::frame_id_is_next as unnecessary
+ Remove the frame_object::frame_id_is_next field. This has been part
+ of how Python handles frames since this code was first added in commit
+ f8f6f20b6e37e6d219940fcad58b1f66124d11c1 back in 2009. The motivation
+ for this field can be found in a couple of comments, there's this one
+ on frame_id_is_next:
+
+ /* Marks that the FRAME_ID member actually holds the ID of the frame next
+ to this, and not this frames' ID itself. This is a hack to permit Python
+ frame objects which represent invalid frames (i.e., the last frame_info
+ in a corrupt stack). The problem arises from the fact that this code
+ relies on FRAME_ID to uniquely identify a frame, which is not always true
+ for the last "frame" in a corrupt stack (it can have a null ID, or the same
+ ID as the previous frame). Whenever get_prev_frame returns NULL, we
+ record the frame_id of the next frame and set FRAME_ID_IS_NEXT to 1. */
+
+ And this one in frame_info_to_frame_object:
+
+ /* Try to get the previous frame, to determine if this is the last frame
+ in a corrupt stack. If so, we need to store the frame_id of the next
+ frame and not of this one (which is possibly invalid). */
+
+ This field is dealing with a problem that was present in older
+ versions of GDB where not every stack frame had a valid frame-id, if
+ the stack was corrupted in some way then the last frame might have an
+ invalid frame-id. However, that is no longer the case. With current
+ GDB there is a promise that every frame has a valid frame-id. I don't
+ have a single commit to point to where this became the reality, but it
+ is my understanding of current GDB.
+
+ As an example, the frame-id of every frame (except #0) is computed as
+ the frame is created, any frames with a duplicate frame-id, or any
+ errors during computation of the frame-id, and the new frame is
+ discarded.
+
+ Additionally, our frame_info_ptr::reinflate mechanism relies on unique
+ and valid frame-ids.
+
+ The problem with the existing code is that the last frame in a
+ corrupted stack will hold the frame-id of the next frame, that is, the
+ more inner frame. This means we have two frames holding the same
+ frame-id, and the only difference is the frame_id_is_next flag.
+
+ However, the frapy_str function, which prints a string representation
+ of the frame, doesn't take frame_id_is_next into account, so printing
+ the last two frames in a corrupted stack, will print the same
+ frame-id.
+
+ We could fix this in frapy_str and also frapy_repr by checking the
+ frame_id_is_next flag and then fetching the previous frame-id, but
+ this would still assume that the previous frame has a valid-id, so we
+ might as well just drop the frame_id_is_next flag and make everything
+ simpler.
+
+ There's a new test which exposes the incorrectly printed frame-id
+ problem.
+
+ While testing I needed to "fix" the results for two existing tests.
+
+ In frame_info_to_frame_object, in order to figure out if we should use
+ the next frame, we called get_prev_frame. This would cause GDB to
+ always unwind 1 extra level of the stack.
+
+ What this means is that, if there is an error, or some diagnostic
+ output, when unwinding frame #1, then this will show up when trying to
+ access frame #0 via the Python API as frame_info_to_frame_object on
+ frame #0 would call get_prev_frame, which would then unwind frame #1.
+
+ After this commit this is no longer the case. We only see
+ output (either errors, or diagnostic output) associated with frame #1
+ when we actually try to unwind to frame #1. The two tests that needed
+ updating were expecting output associated with frame #1 while printing
+ frame #0. This is now fixed and the output for frame #1 occurs later
+ on. I think this is an improvement.
+
+2026-07-08 Andrew Burgess <aburgess@redhat.com>
+
+ gdb/testsuite: don't overwrite test executable in py-frame.exp
+ In gdb.python/py-frame.exp when we re-compile the test executable
+ without debug information, give it a new, unique, name to make
+ re-running the tests outside the testsuite easier.
+
+ While I was in the area I removed a `gdb_exit` call that was not
+ necessary, `prepare_for_testing` calls `clean_restart` which already
+ does a `gdb_exit`.
+
+ There should be no change in what is being tested after this commit.
+
+2026-07-08 GDB Administrator <gdbadmin@sourceware.org>
+
+ Automatic date update in version.in
+
+2026-07-07 Keith Seitz <keiths@redhat.com>
+
+ [gdbserver] Use const_target_desc_up for regformat tdescs
+ Regformat tdescs are now declared 'const_target_desc_up' by
+ gdb's regdat.sh, so update the various gdbserver target descriptions
+ to observe this API change.
+
+ There should be no user visible changes.
+
+ Approved-By: Simon Marchi <simon.marchi@efficios.com>
+
+2026-07-07 Keith Seitz <keiths@redhat.com>
+
+ regdat.sh: generate const_target_desc_up for register descriptions
+ Late last year, a patch propagated the use of target_desc unique
+ pointers (commit 1a5362ce51ef79ffb61caa20c93284dc368dc74a). At the
+ time, the "old regformats/regdat.sh [weren't] changed because their
+ target_desc objects are statically allocated in the generated files."
+
+ Unfortunately that re-introduced ODR violations on ppc64le:
+
+ CXXLD gdbserver
+ ../../src/gdbserver/../gdb/arch/ppc-linux-tdesc.h:46:29: error: ‘tdesc_powerpc_isa207_htm_vsx64l’ violates the C++ One Definition Rule [-Werror=odr]
+ 46 | extern const_target_desc_up tdesc_powerpc_isa207_htm_vsx64l;
+ | ^
+ powerpc-isa207-htm-vsx64l-generated.cc:26:27: note: ‘tdesc_powerpc_isa207_htm_vsx64l’ was previously declared here
+ 26 | const struct target_desc *tdesc_powerpc_isa207_htm_vsx64l;
+ | ^
+ powerpc-isa207-htm-vsx64l-generated.cc:26:27: note: code may be misoptimized unless ‘-fno-strict-aliasing’ is used
+
+ Update regdat.sh so that generated init_registers_* code matches the
+ const-unique_ptr-based target description API, resolving the ODR violation.
+
+ A follow-up patch updates various gdbserver architectures to
+ accommodate this API change.
+
+ Tested on ppc64le and s390x Fedora 43 and mips-linux
+ cross build (all with LTO).
+
+ Approved-By: Simon Marchi <simon.marchi@efficios.com>
+ Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=28444
+
+2026-07-07 Simon Marchi <simon.marchi@efficios.com>
+
+ gdb/record-full: make record_full_arch_list_add take an rvalue ref
+ record_full_arch_list_add moves its `rec` argument, so it should take an
+ rvalue ref to reflect that. Otherwise the fact that the object is moved
+ from can be a "surprise" to the callers.
+
+ Change-Id: Ibeb56b1523ad8aee077d3bc3cad1f00d6b47ea2f
+ Approved-By: Guinevere Larsen <guinevere@redhat.com>
+
+2026-07-07 Alan Modra <amodra@gmail.com>
+
+ Check the result of two bfd_alloc calls in elf.c
+ PR 34131
+ * elf.c: Remove unnecessary casts on bfd_[zm]*alloc return value.
+ Do without "amt" temp var in a few cases.
+ (assign_section_numbers): Check for NULL return from bfd_zalloc.
+ (elfobj_grok_stapsdt_note_1): Likewise for bfd_alloc.
+
+ Re: LoongArch: Fix relaxation alignment with ld -r (PR 33236)
+ Correct sh_size and sh_entsize to use external reloc size.
+ loongarch32-elf +FAIL: Linkonce sections with assembler generated notes
+ loongarch32-elf +FAIL: ld-loongarch-elf/relax-align-ld-r
+
+2026-07-07 Alan Modra <amodra@gmail.com>
+
+ alpha, rl78, rx: UB in reloc handling
+ This patch avoids undefined behaviour and divide by zero exceptions in
+ some relocation processing. In most cases, unsigned arithmetic is
+ used which has defined overflow characteristics. Arithmetic right
+ shift, division, and modulo operations have more special cases. See
+ the explanation in commit 30200464e9dd.
+
+ * coff-alpha.c (alpha_ecoff_get_relocated_section_contents): Avoid
+ UB in RSHIFT reloc.
+ (alpha_relocate_section): Likewise.
+ * elf32-rl78.c (rl78_compute_complex_reloc): Avoid UB in reloc
+ arithmetic.
+ * elf32-rx.c (rx_elf_relocate_section): Likewise.
+ (rx_offset_for_reloc): Likewise.
+
+2026-07-07 Alan Modra <amodra@gmail.com>
+
+ Re: gas: add --reloc-section-sym option
+ * testsuite/gas/elf/reloc-section-sym-none.d: Accept mips64 relocs.
+
+2026-07-07 Alan Modra <amodra@gmail.com>
+
+ PR 34353 objcopy: null-pointer dereference bfd/section.c:1433
+ objcopy --update-section specifying a SHT_GROUP section hits a case
+ where output_section is NULL.
+
+ * objcopy.c (copy_object): Don't segfault when update_sections
+ output_section is NULL. Remove the "not found" part of
+ existing error so this message can be used.
+ * testsuite/binutils-all/update-section.exp: Update to suit.
+
+2026-07-07 GDB Administrator <gdbadmin@sourceware.org>
+
+ Automatic date update in version.in
+
+2026-07-06 Pedro Alves <pedro@palves.net>
+
+ Windows/rocm-solib: Don't hardcode namespaces support
+ rocm_solib_ops currently unconditionally returns true to
+ solib_ops::supports_namespaces. That works OK on Linux where the
+ underlying solib ops is svr4. But on Windows, the underlying solib
+ ops is solib-target, which does not support namespaces. The result
+ is:
+
+ (gdb) info shared
+ /home/pedro/rocm/gdb/build/gdb/solib.h:270: internal-error: num_active_namespaces: namespaces not supported
+ A problem internal to GDB has been detected,
+ further debugging may prove unreliable.
+ ...
+ Thread 1 hit Breakpoint 1, internal_verror (file=0x7ff71a27fc80 <SCRIPTING_SEARCH_FLAG+52> "/home/pedro/rocm/gdb/build/gdb/solib.h", line=270,
+ fmt=0x7ff71a27fc5e <SCRIPTING_SEARCH_FLAG+18> "%s: namespaces not supported", ap=0xfff1a8 "\270\374'", <incomplete sequence \367\177>)
+ at /home/pedro/rocm/gdb/build/gdb/utils.c:514
+ 514 internal_vproblem (&internal_error_problem, file, line, fmt, ap);
+ (gdb) bt
+ #0 internal_verror (file=0x7ff71a27fc80 <SCRIPTING_SEARCH_FLAG+52> "/home/pedro/rocm/gdb/build/gdb/solib.h", line=270,
+ fmt=0x7ff71a27fc5e <SCRIPTING_SEARCH_FLAG+18> "%s: namespaces not supported", ap=0xfff1a8 "\270\374'", <incomplete sequence \367\177>)
+ at /home/pedro/rocm/gdb/build/gdb/utils.c:514
+ #1 0x00007ff719c75cf4 in internal_error_loc (file=0x7ff71a27fc80 <SCRIPTING_SEARCH_FLAG+52> "/home/pedro/rocm/gdb/build/gdb/solib.h", line=270,
+ fmt=0x7ff71a27fc5e <SCRIPTING_SEARCH_FLAG+18> "%s: namespaces not supported") at /home/pedro/rocm/gdb/build/gdbsupport/errors.cc:57
+ #2 0x00007ff719f0aafe in solib_ops::num_active_namespaces (this=0xbb3a0b0) at /home/pedro/rocm/gdb/build/gdb/solib.h:270
+ #3 0x00007ff719eca99e in rocm_solib_ops::num_active_namespaces (this=0xc9388a0) at /home/pedro/rocm/gdb/build/gdb/solib-rocm.c:211
+ #4 0x00007ff719a14d33 in print_solib_list_table (solib_list=..., print_namespace=true) at /home/pedro/rocm/gdb/build/gdb/solib.c:1011
+ #5 0x00007ff719a15833 in info_sharedlibrary_command (pattern=0x0, from_tty=1) at /home/pedro/rocm/gdb/build/gdb/solib.c:1115
+
+ rocm_solib_ops will stop sitting on top of another solib
+ implementation once the multi solib provider work lands, but
+ meanwhile, it'd be helpful to not crash.
+
+ Fix this by making rocm_solib_ops::supports_namespaces() delegate to
+ the underlying host solib ops like other methods do.
+
+ Approved-by: Lancelot Six <lancelot.six@amd.com> (amdgpu)
+ Change-Id: I1627c6e2f1b1c171c013c8457e9bfca92d5f4dc5
+
+2026-07-06 Pedro Alves <pedro@palves.net>
+
+ gdb.rocm: Don't include unistd.h when not necessary
+ gdb.rocm/code-object-load-while-breakpoint-hit.cpp is including
+ unistd.h unnecessarily AFAICS. Don't include it, so this test can
+ compile on Windows (x86_64-pc-windows-msvc) as well.
+
+ Approved-by: Lancelot Six <lancelot.six@amd.com> (amdgpu)
+ Change-Id: I9f469fd4b061ab9895c8bbbd408939e4df2a4e92
+
+2026-07-06 Pedro Alves <pedro@palves.net>
+
+ gdb.rocm/multi-inferior-gpu.exp: Use allow_fork_tests
+ The program of gdb.rocm/multi-inferior-gpu.exp uses fork, so make the
+ testcase require allow_fork_tests.
+
+ Approved-by: Lancelot Six <lancelot.six@amd.com> (amdgpu)
+ Change-Id: I4c762be8d19c168f15962c68f8cbcc22ec3d6556
+
+2026-07-06 Pedro Alves <pedro@palves.net>
+
+ Windows: Normalize backslashes to forward slashes
+ Currently, on native Windows, GDB presents a mix of backslashes and
+ forward slashes to users, like e.g.:
+
+ ...
+ attach 15044
+ Attaching to program: C:\msys2\home\alves\gdb\build-testsuite\outputs\gdb.base\attach\attach.exe, process 15044
+ ...
+ [Switching to thread 1 (Thread 15044.0x1294)]
+ main () at C:/rocgdb/src/gdb/testsuite/gdb.base/attach.c:19
+ 19 while (! should_exit)
+ (gdb) FAIL: gdb.base/attach.exp: do_attach_failure_tests: first attach
+ ...
+
+ Note how above, the "attach" command uses backslashes, and the source
+ path uses forward slashes.
+
+ Most annoyingly, depending on compiler, you can end up with mixed
+ slash styles in the same path:
+
+ Temporary breakpoint 1 at 0x1400010ec: file C:/rocgdb/src/gdb/testsuite/gdb.rocm\simple.cpp, line 33.
+ ^
+
+ A while ago, in commit a63213cd37 ("MSYS2+MinGW testing: Unix <->
+ Windows path conversion"), I had made the testsuite normalize
+ backslashes to forward slashes, among other things. I had said in the
+ commit log there:
+
+ "It's arguable whether GDB itself should do this sanitization. I
+ suspect it should. I personally dislike seeing backward slashes in
+ e.g., "info shared" output, or worse, mixed backward and forward
+ slashes. Still, I propose starting with a testsuite adjustment that
+ moves us forward, and handle that separately. I won't be surprised if
+ we need the new routine for some cases even if we adjust GDB."
+
+ After running into some other tests that would need backslash
+ adjustment, and also because this is something user-visible, not just
+ a testsuite issue, I decided to bite the bullet and make GDB itself do
+ the slashes normalization.
+
+ This patch fixes all the cases of backslashes that I could find:
+
+ - source files and compilation directory
+ - executable name, and shared library names
+ - cd/pwd commands
+
+ It does this by normalizing slashes at some strategic places. The
+ conversion is only attempted if needed -- i.e., if debugging on
+ Windows, or cross-debugging Windows programs from a non-Windows host.
+
+ For executable/shared library names, this is doing the backslash ->
+ forward slash conversion completely on the host side in common code,
+ without touching the target backend files in either GDB or GDBserver,
+ by design, so that this is all completely a client side decision, and
+ works the same against any Windows GDBserver version, against remote
+ servers other than ours (e.g., Wine's), so we can change it later if
+ we want, etc.
+
+ I did tweak the gdb and gdbserver backends for the other way around
+ (forward slash => backslash), to make sure that they pass backslashes
+ to CreateProcess, so that inferiors see native backslashes in their
+ own argv[0]. For GDBserver, it would already have been possible to
+ launch an executable with forward slashes before (e.g., when debugging
+ from a Linux or Cygwin client), so this makes Windows gdbserver
+ behavior more consistent, independently of client, too.
+
+ I did not add an option to make this configurable at runtime on
+ purpose. I don't see the point, it'd just add more complication and
+ testing surface. Always normalizing keeps it simple.
+
+ For the source paths, I considered doing the normalization earlier in
+ the DWARF reader, but decided against it, because that would force
+ extra copying of strings -- the DWARF reader works mostly by passing
+ around const char pointers. Also, the places I picked in principle
+ will automatically handle PDB if/when we get to it.
+
+ The buildsym.c change takes care of compilation directory paths.
+
+ The allocate_symtab change takes care of source paths. That one
+ required a (temporary) copy, but I think that that's acceptable there.
+
+ The gdb_realpath change is needed because just before the touched code
+ there's a GetFullPathName call, which itself normalizes to
+ backslashes.
+
+ The exec.c and solib.c changes take care of executable and shared
+ libraries.
+
+ The change to testsuite/lib/gdb.exp, to adjust to forward-slash style
+ for DOS full names, are necessary otherwise MI tests break. E.g.:
+
+ *stopped,reason="breakpoint-hit",disp="del",bkptno="1",frame={addr="0x00007ff780461508",
+ func="main",args=[],file="C:/rocgdb/src/gdb/testsuite/gdb.mi/basics.c",
+ fullname="C:/rocgdb/src/gdb/testsuite/gdb.mi/basics.c",line="64",arch="i386:x86-64"},
+ thread-id="1",stopped-threads="all"
+ FAIL: gdb.mi/gdb2549.exp: mi runto main (unknown output after running)
+
+ gdb.base/set-cwd.exp was the only test I found (so far at least) that
+ required adjustment, but note that without this patch that testcase
+ fails and throws TCL errors, like:
+
+ ...
+ FAIL: gdb.base/set-cwd.exp: test_cwd_reset: inferior cwd is correctly set
+ ERROR: couldn't compile regular expression pattern: invalid escape \ sequence
+ ...
+
+ It passes cleanly with the patch.
+
+ Below's the before / after comparison of different commands / output.
+
+ Before:
+
+ Reading symbols from ./outputs/gdb.rocm/simple/simple...
+ (gdb)
+ start
+ Temporary breakpoint 1 at 0x1400010ec: file C:/rocgdb/src/gdb/testsuite/gdb.rocm\simple.cpp, line 33.
+ Starting program: C:\msys2\home\alves\gdb\build-testsuite\outputs\gdb.rocm\simple\simple
+
+ Thread 1 hit Temporary breakpoint 1, main () at C:/rocgdb/src/gdb/testsuite/gdb.rocm\simple.cpp:33
+ 33 hipError_t error = hipMalloc (&result_ptr, sizeof (int));
+
+ Thread 1 hit Temporary breakpoint 1, main () at C:/rocgdb/src/gdb/testsuite/gdb.rocm\simple.cpp:33
+ 33 hipError_t error = hipMalloc (&result_ptr, sizeof (int));
+ (gdb)
+
+ (gdb) info inferiors
+ Num Description Connection Executable
+ * 1 process 15620 1 (native) C:\msys2\home\alves\gdb\build-testsuite\outputs\gdb.rocm\simple\simple
+
+ (gdb) info sharedlibrary
+ From To Syms Read Shared Object Library
+ 0x00007ffd22f91000 0x00007ffd231a69a8 Yes (*) C:\Windows\SYSTEM32\ntdll.dll
+ 0x00007ffd21af1000 0x00007ffd21bb2520 Yes (*) C:\Windows\System32\kernel32.dll
+ 0x00007ffd20091000 0x00007ffd20432548 Yes (*) C:\Windows\System32\KernelBase.dll
+ 0x00007ffcc89c1000 0x00007ffcc9b145bc Yes (*) C:\Windows\SYSTEM32\amdhip64_7.dll
+ 0x00007ffd22911000 0x00007ffd22d829b0 Yes (*) C:\Windows\System32\setupapi.dll
+ 0x00007ffd216c1000 0x00007ffd217653f0 Yes (*) C:\Windows\System32\msvcrt.dll
+ 0x00007ffd22431000 0x00007ffd224de5c8 Yes (*) C:\Windows\System32\advapi32.dll
+ 0x00007ffd21a41000 0x00007ffd21ae52b8 Yes (*) C:\Windows\System32\sechost.dll
+ 0x00007ffd20651000 0x00007ffd20676af0 Yes (*) C:\Windows\System32\bcrypt.dll
+ 0x00007ffd21f31000 0x00007ffd22045860 Yes (*) C:\Windows\System32\rpcrt4.dll
+ 0x00007ffd22d91000 0x00007ffd22f40e50 Yes (*) C:\Windows\System32\user32.dll
+ 0x00007ffd20781000 0x00007ffd207a43d8 Yes (*) C:\Windows\System32\win32u.dll
+ 0x00007ffd228d1000 0x00007ffd228f73d8 Yes (*) C:\Windows\System32\gdi32.dll
+ 0x00007ffd207b1000 0x00007ffd208d09c8 Yes (*) C:\Windows\System32\gdi32full.dll
+ 0x00007ffd20b91000 0x00007ffd20c28410 Yes (*) C:\Windows\System32\msvcp_win.dll
+ 0x00007ffd20471000 0x00007ffd2057f410 Yes (*) C:\Windows\System32\ucrtbase.dll
+ 0x00007ffd21541000 0x00007ffd215afbc8 Yes (*) C:\Windows\System32\ws2_32.dll
+ 0x00007ffd223f1000 0x00007ffd2241fc40 Yes (*) C:\Windows\System32\imm32.dll
+
+ (gdb) info source
+ Current source file is C:/rocgdb/src/gdb/testsuite/gdb.rocm\simple.cpp
+ Compilation directory is C:\msys2\home\alves\gdb\build-testsuite
+ Located in C:\rocgdb\src\gdb\testsuite\gdb.rocm\simple.cpp
+
+ (gdb) info sources
+ C:\msys2\home\alves\gdb\build-testsuite\outputs\gdb.rocm\simple\simple:
+
+ C:\rocgdb\src\gdb\testsuite\gdb.rocm\simple.cpp, C:\Program Files (x86)\Windows Kits\10\Include\10.0.22621.0\ucrt\corecrt_stdio_config.h,
+ C:\Program Files\AMD\ROCm\7.1\include\hip\hip_runtime_api.h, C:\Program Files\Microsoft Visual Studio\2022\Community\VC\Tools\MSVC\14.39.33519\include\stdint.h,
+ C:\Program Files (x86)\Windows Kits\10\Include\10.0.22621.0\ucrt\stdio.h, C:\Program Files\AMD\ROCm\7.1\lib\clang\21\include\__stddef_nullptr_t.h,
+ C:\Program Files\AMD\ROCm\7.1\lib\clang\21\include\__stddef_size_t.h, C:\Program Files\Microsoft Visual Studio\2022\Community\VC\Tools\MSVC\14.39.33519\include\cstdlib,
+ C:\Program Files (x86)\Windows Kits\10\Include\10.0.22621.0\ucrt\stdlib.h, C:\Program Files (x86)\Windows Kits\10\Include\10.0.22621.0\ucrt\corecrt_search.h,
+ C:\Program Files (x86)\Windows Kits\10\Include\10.0.22621.0\ucrt\corecrt_malloc.h,
+ ...
+
+ (gdb) detach
+ Detaching from program: C:\msys2\home\alves\gdb\build-testsuite\outputs\gdb.rocm\simple\simple, process 20800
+ [Inferior 1 (process 20800) detached]
+
+ (gdb) cd /tmp
+ Working directory C:\tmp.
+ (gdb) pwd
+ Working directory C:\tmp.
+
+ After:
+
+ Reading symbols from ./outputs/gdb.rocm/simple/simple...
+ (gdb) start
+ Temporary breakpoint 1 at 0x1400010ec: file C:/rocgdb/src/gdb/testsuite/gdb.rocm/simple.cpp, line 33.
+ Starting program: C:/msys2/home/alves/gdb/build-testsuite/outputs/gdb.rocm/simple/simple
+
+ Thread 1 hit Temporary breakpoint 1, main () at C:/rocgdb/src/gdb/testsuite/gdb.rocm/simple.cpp:33
+ 33 hipError_t error = hipMalloc (&result_ptr, sizeof (int));
+
+ (gdb) info sources
+ C:/msys2/home/alves/gdb/build-testsuite/outputs/gdb.rocm/simple/simple:
+
+ C:/rocgdb/src/gdb/testsuite/gdb.rocm/simple.cpp, C:/Program Files (x86)/Windows Kits/10/Include/10.0.22621.0/ucrt/corecrt_stdio_config.h,
+ C:/Program Files/AMD/ROCm/7.1/include/hip/hip_runtime_api.h, C:/Program Files/Microsoft Visual Studio/2022/Community/VC/Tools/MSVC/14.39.33519/include/stdint.h,
+ C:/Program Files (x86)/Windows Kits/10/Include/10.0.22621.0/ucrt/stdio.h, C:/Program Files/AMD/ROCm/7.1/lib/clang/21/include/__stddef_nullptr_t.h,
+ C:/Program Files/AMD/ROCm/7.1/lib/clang/21/include/__stddef_size_t.h, C:/Program Files/Microsoft Visual Studio/2022/Community/VC/Tools/MSVC/14.39.33519/include/cstdlib,
+ C:/Program Files (x86)/Windows Kits/10/Include/10.0.22621.0/ucrt/stdlib.h, C:/Program Files (x86)/Windows Kits/10/Include/10.0.22621.0/ucrt/corecrt_search.h,
+ C:/Program Files (x86)/Windows Kits/10/Include/10.0.22621.0/ucrt/corecrt_malloc.h,
+ ...
+
+ (gdb) info inferiors
+ Num Description Connection Executable
+ * 1 process 19920 1 (native) C:/msys2/home/alves/gdb/build-testsuite/outputs/gdb.rocm/simple/simple
+
+ (gdb) info shared
+ From To Syms Read Shared Object Library
+ 0x00007ffd22f91000 0x00007ffd231a69a8 Yes (*) C:/Windows/SYSTEM32/ntdll.dll
+ 0x00007ffd21af1000 0x00007ffd21bb2520 Yes (*) C:/Windows/System32/kernel32.dll
+ 0x00007ffd20091000 0x00007ffd20432548 Yes (*) C:/Windows/System32/KernelBase.dll
+ 0x00007ffcc89c1000 0x00007ffcc9b145bc Yes (*) C:/Windows/SYSTEM32/amdhip64_7.dll
+ 0x00007ffd22911000 0x00007ffd22d829b0 Yes (*) C:/Windows/System32/setupapi.dll
+ 0x00007ffd216c1000 0x00007ffd217653f0 Yes (*) C:/Windows/System32/msvcrt.dll
+ 0x00007ffd22431000 0x00007ffd224de5c8 Yes (*) C:/Windows/System32/advapi32.dll
+ 0x00007ffd21a41000 0x00007ffd21ae52b8 Yes (*) C:/Windows/System32/sechost.dll
+ 0x00007ffd20651000 0x00007ffd20676af0 Yes (*) C:/Windows/System32/bcrypt.dll
+ 0x00007ffd21f31000 0x00007ffd22045860 Yes (*) C:/Windows/System32/rpcrt4.dll
+ 0x00007ffd22d91000 0x00007ffd22f40e50 Yes (*) C:/Windows/System32/user32.dll
+ 0x00007ffd20781000 0x00007ffd207a43d8 Yes (*) C:/Windows/System32/win32u.dll
+ 0x00007ffd228d1000 0x00007ffd228f73d8 Yes (*) C:/Windows/System32/gdi32.dll
+ 0x00007ffd207b1000 0x00007ffd208d09c8 Yes (*) C:/Windows/System32/gdi32full.dll
+ 0x00007ffd20b91000 0x00007ffd20c28410 Yes (*) C:/Windows/System32/msvcp_win.dll
+ 0x00007ffd20471000 0x00007ffd2057f410 Yes (*) C:/Windows/System32/ucrtbase.dll
+ 0x00007ffd21541000 0x00007ffd215afbc8 Yes (*) C:/Windows/System32/ws2_32.dll
+ 0x00007ffd223f1000 0x00007ffd2241fc40 Yes (*) C:/Windows/System32/imm32.dll
+ (*): Shared library is missing debugging information.
+
+ (gdb) detach
+ Detaching from program: C:/msys2/home/alves/gdb/build-testsuite/outputs/gdb.rocm/simple/simple, process 7816
+ [Inferior 1 (process 7816) detached]
+
+ (gdb) cd /tmp
+ Working directory C:/tmp.
+ (gdb) pwd
+ Working directory C:/tmp.
+
+ Reviewed-By: Eli Zaretskii <eliz@gnu.org>
+ Reviewed-By: Andrew Burgess <aburgess@redhat.com>
+ Change-Id: I6366c41d200938259330e60bc1e98b576f787518
+
+2026-07-06 Simon Marchi <simon.marchi@efficios.com>
+
+ gdb/record-full: fix some -Wpessimizing-move errors
+ Compiling record-full.c with clang shows:
+
+ /home/smarchi/src/binutils-gdb/gdb/record-full.c:2386:14: error: moving a temporary object prevents copy elision [-Werror,-Wpessimizing-move]
+ 2386 | rec.entry = std::move (record_full_reg_entry::from_bfd
+ | ^
+ /home/smarchi/src/binutils-gdb/gdb/record-full.c:2386:14: note: remove std::move call here
+ 2386 | rec.entry = std::move (record_full_reg_entry::from_bfd
+ | ^~~~~~~~~~~
+ 2387 | (cbfd, osec, bfd_offset));
+ | ~
+ /home/smarchi/src/binutils-gdb/gdb/record-full.c:2393:14: error: moving a temporary object prevents copy elision [-Werror,-Wpessimizing-move]
+ 2393 | rec.entry = std::move (record_full_mem_entry::from_bfd
+ | ^
+ /home/smarchi/src/binutils-gdb/gdb/record-full.c:2393:14: note: remove std::move call here
+ 2393 | rec.entry = std::move (record_full_mem_entry::from_bfd
+ | ^~~~~~~~~~~
+ 2394 | (cbfd, osec, bfd_offset));
+ | ~
+
+ It's indeed not recommended to std::move the return value of a
+ function. Remove the std::moves.
+
+ Change-Id: I80d947aa3d917fe3fcaaad0c3e329cb1de48a8ee
+
+2026-07-06 Jens Remus <jremus@linux.ibm.com>
+
+ s390: Deprecate s390 32-bit target "s390-*"
+ The s390 32-bit target (s390-*) is deprecated and planned for removal
+ in a future release, along with the elf32-s390 target format. Emit an
+ error for this target during configure, which can be overridden using
+ option --enable-obsolete.
+
+ Linux Kernel 6.19 removed s390 32-bit compatibility support. [1]
+ Glibc 2.43 [2] and GCC 16.1 (compiler option -m31) [3] deprecated
+ s390 32-bit with the intent to remove it in a future release.
+
+ The s390 64-bit target (s390x-*) remains supported.
+
+ [1]: Linux kernel 6.19 commit 8e0b986c59c6 ("s390: Remove compat support"),
+ https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=8e0b986c59c6
+ [2]: Glibc 2.43 commit 638d437dbf9c ("Deprecate s390-linux-gnu (31bit)"),
+ https://sourceware.org/git/glibc.git?a=commitdiff;h=638d437dbf9c
+ [3]: GCC 16 commit 5886bb453a6a ("s390: Deprecate -m31"),
+ https://gcc.gnu.org/git/gcc.git?h=5886bb453a6a
+
+ bfd/
+ * config.bfd: Require --enable-obsolete to build s390 32-bit
+ target "s390-*".
+
+ binutils/
+ * NEWS: Deprecate s390 32-bit target "s390-*".
+
+ gdb/
+ * NEWS: Deprecate s390 32-bit target "s390-*".
+
+2026-07-06 Jens Remus <jremus@linux.ibm.com>
+
+ s390: Add store CPU counter multiple instruction
+ IBM z13 introduced the "store CPU counter multiple" (stcctm) instruction
+ with the Store-CPU-Counter-Multiple Facility, which is part of the
+ CPU-Measurement Facilities (CPUMF) [1].
+
+ While at it add a comment to the s390 opcode table for the existing
+ CPUMF instructions.
+
+ [1]: The Load-Program-Parameter and the CPU-Measurement Facilities,
+ SA23-2260-08,
+ https://www.ibm.com/docs/en/module_1678991624569/pdf/SA23-2260-08.pdf
+
+ opcodes/
+ * s390-opc.txt (stcctm): Add store CPU counter multiple
+ instruction. Add comment on CPUMF instructions.
+
+ gas/testsuite/
+ * gas/s390/zarch-z13.d (stcctm): Add test for store CPU counter
+ multiple instruction.
+ * gas/s390/zarch-z13.s (stcctm): Likewise.
+
+2026-07-06 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
+
+ aarch64: Fix assembler internal error for %dtprel relocations
+ The current implementation creates the DTPREL fixup before reserving
+ the storage for the corresponding ".xword". GCC's "%dtprel" support
+ for TLS DWARF debug information exposed this during an AArch64 bootstrap,
+ where the libsanitizer/tsan DWARF layout places the DTPREL fixup at a
+ frag boundary. Reserving the storage before creating the fixup avoids
+ this corner case.
+
+ gas/
+ PR binutils/34357
+ * config/tc-aarch64.c (s_aarch64_cons) : Fix the storage order for
+ DTPREL.
+
+2026-07-06 Tankut Baris Aktemur <tankutbaris.aktemur@amd.com>
+
+ gdb, amd-dbgapi-target: split wave_coordinates::to_string
+ wave_coordinates::to_string() produces a string in the following format:
+
+ AMDGPU Wave a:q:d:w (x,y,z)/i
+
+ Split the method into smaller pieces:
+
+ a:q:d:w : hierarchy_str
+ (x,y,z) : workgroup_coord_str
+ (x,y,z)/i : dispatch_pos_str
+
+ This is a refactoring to allow reusing pieces and also to let the code
+ document itself better. Currently the reuse opportunity exists in the
+ downstream debugger.
+
+ Approved-By: Simon Marchi <simon.marchi@efficios.com>
+ Approved-by: Lancelot Six <lancelot.six@amd.com> (amdgpu)
+
+2026-07-06 Tankut Baris Aktemur <tankutbaris.aktemur@amd.com>
+
+ gdb, amd-dbgapi-target: use pulongest more
+ The group id coordinates and the wave number in workgroup that are
+ being formatted to a string in wave_coordinates::to_string are
+ uint32_t. Use pulongest to print them.
+
+ Approved-by: Lancelot Six <lancelot.six@amd.com> (amdgpu)
+
+2026-07-05 mengqinggang <mengqinggang@loongson.cn>
+
+ LoongArch: Fix relaxation alignment with ld -r (PR 33236)
+ LoongArch has the same issue as RISC-V for PR 33236 [1].
+
+ Section alignment can't be adjusted for objects generated by ld -r.
+ If previous sections are relaxed, the subsequent section maybe misaligned.
+
+ To fix this, add an align section and an align relocation before each
+ section when ld -r. And change the section alignment to 4 to disable
+ the default section start address calculation.
+
+ ld.lld has fixed this issue in the following two patches [2] [3].
+
+ [1] https://sourceware.org/bugzilla/show_bug.cgi?id=33236
+ [2] https://github.com/llvm/llvm-project/pull/151639
+ [3] https://github.com/llvm/llvm-project/pull/198147
+
+2026-07-05 mengqinggang <mengqinggang@loongson.cn>
+
+ LoongArch: Fix linker relaxation alignment
+ When linking multiple objects, relaxation can cause alignment issues.
+ Input section's output_offset is updated in relaxation without considering
+ alignment. Update section output_offset by align_opwer.
+
+2026-07-06 GDB Administrator <gdbadmin@sourceware.org>
+
+ Automatic date update in version.in
+
+2026-07-05 Fangrui Song <maskray@sourceware.org>
+
+ gas: add --reloc-section-sym={all,internal,none} option for ELF
+ When generating relocations for non-ifunc local symbols that satisfies
+ several conditions, GAS converts them to reference the section symbol
+ (STT_SECTION) instead, folding the original symbol's offset into the
+ addend. This allows the original local symbol to be omitted from
+ .symtab, but the STT_SECTION symbol itself must be present, so the
+ conversion saves .symtab entries only when a section has more than one
+ local symbol referenced by relocations.
+
+ Add --reloc-section-sym to control this conversion:
+
+ - all (default): convert all eligible local symbols
+ - internal: only convert compiler-generated locals (.L prefix)
+ - none: never convert; keep all symbols as-is in relocations
+
+ This is useful for debugging and for tools that benefit from preserved
+ symbol names.
+
+ PR gas/33885
+
+2026-07-05 GDB Administrator <gdbadmin@sourceware.org>
+
+ Automatic date update in version.in
+
+2026-07-04 Alan Modra <amodra@gmail.com>
+
+ pr34322: assertion failure in get_or_create_member_type
+ I thought about warning "DW_TAG_member without struct/union parent"
+ here but decided that doesn't help much as the warning is disconnected
+ from output. As it is the --map-global-vars code silently ignores
+ unexpected attributes that might be found in fuzzed files. I'm fine
+ with that too.
+
+ PR 34322
+ * dwarf.c (get_or_create_member_type): Return NULL on NULL parent.
+ (insert_element_in_list): Ignore DW_TAG_member without struct
+ or union parent.
+
+2026-07-04 Georg-Johann Lay <avr@gjlay.de>
+
+ AVR: Adhere to GNU coding style
+ This patch fixes some style nits:
+
+ - Fix indentations
+ - Using TABs for indentation
+ - Breaking long lines
+ - Remove ; after the closing } of a code block
+
+ bfd/
+ * cpu-avr.c: Adhere to GNU coding style.
+ * elf32-avr.c: Same.
+ * elf32-avr.h: Same.
+
+ gas/
+ * config/tc-avr.c: Adhere to GNU coding style.
+
+ opcodes/
+ * avr-dis.c: Adhere to GNU coding style.
+
+ include/
+ * opcode/avr.h: Adhere to GNU coding style.
+
+2026-07-04 GDB Administrator <gdbadmin@sourceware.org>
+
+ Automatic date update in version.in
+
+2026-07-04 xuqing yang <rigelyoung@icloud.com>
+
+ PR 34275 double free in ctf_link_deduplicating_per_cu
+ * ctf-link.c (ctf_link_deduplicating_per_cu): Don't call
+ ctf_next_destroy twice on error path.
+
+2026-07-03 Guinevere Larsen <guinevere@redhat.com>
+
+ gdb/record: add support for BMI2 instructions
+ This commit adds support for recording all instructions in the Bit
+ Manipulation Instruction set 2, for x86 cpus. The specific instructions
+ are:
+
+ * mulx
+ * pdep
+ * pext
+ * rorx
+ * sarx
+ * sh[r|l]x
+ * bzhi
+
+ And adds them to the AVX test, for the same reason as the previous
+ commit.
+
+ Approved-By: Guinevere Larsen <guinevere@redhat.com>
+
+2026-07-03 Guinevere Larsen <guinevere@redhat.com>
+
+ gdb/record: Add support for recording BMI1 instructions
+ This commit adds support for recording all instructions of the Bit
+ Manipulation Instruction set 1, for x86 cpus. The specific instructions
+ are:
+
+ * andn
+ * bls[i|r|msk]
+ * bextr
+ * [l|t]zcnt
+
+ Also add them to the avx test. While BMI is a different set of
+ instructions, there are no currently existing CPUs that have access to
+ AVX2 and don't have access to BMI1 and BMI2, so it seems like a
+ reasonable idea to keep them together, as the avx test already requires
+ AVX2.
+
+ Approved-By: Guinevere Larsen <guinevere@redhat.com>
+
+2026-07-03 H.J. Lu <hjl.tools@gmail.com>
+
+ readelf: Update dynamic tag processing and validate section info
+ Count DT_RELR relocations using dynamic tags when section header isn't
+ used. Ignore section sh_offset and sh_size if they are larger than file
+ size.
+
+ One side effect is that we now display
+
+ readelf: Warning: Ignore the out of range sh_offset value of 2199023261148 for section 17
+ readelf: Warning: Ignore the out of range sh_size value of 13 for section 17 with sh_offset value of 2199023261148
+ ...
+ [17] .fini PROGBITS 00000000000015dc 000000 000000 00 AX 0 0 4
+ ...
+
+ instead of
+
+ ...
+ [17] .fini PROGBITS 00000000000015dc 200000015dc 00000d 00 AX 0 0 4
+ ...
+
+ and segfault.
+
+ binutils/
+
+ PR binutils/34326
+ PR binutils/34339
+ * readelf.c (update_all_relocations): Skip if nentries == 0.
+ (validate_section_info): New.
+ (get_32bit_section_headers): Call validate_section_info.
+ (get_64bit_section_headers): Likewise.
+ (process_relocs): Call count_relr_relocations for relocations
+ from dynamic tags. Skip if values in DT_RELENT/DT_RELAENT
+ are larger than values in DT_RELSZ/DT_RELASZ.
+ (process_got_section_contents): Skip if all_relocations_count
+ == 0.
+
+ ld/
+ PR binutils/34339
+ * testsuite/ld-x86-64/binutils.exp: Run PR binutils/34339 tests.
+ * testsuite/ld-x86-64/got-2.s: New file.
+ * testsuite/ld-x86-64/libgot-2.rd: Likewise.
+
+2026-07-03 Guinevere Larsen <guinevere@redhat.com>
+
+ gdb/record: rename record_full_list to record_full_log
+ Now that we no longer use a linked list to manage the history, the name
+ "record_full_list" is no longer meaningful. This commit changes the name
+ to record_full_log since it is the execution log. I decided to not say
+ "record_full_execution_log" to avoid overly long lines when accessing
+ it.
+
+ Reviewed-by: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
+ Reviewed-By: Christina Schimpe <christina.schimpe@intel.com>
+ Approved-By: Guinevere Larsen <guinevere@redhat.com>
+
+2026-07-03 Guinevere Larsen <guinevere@redhat.com>
+
+ gdb/record: Define new version of the record-save section
+ With the changes to the internal representation of the history, we can
+ no longer support the previous record save format. This commit makes it
+ official, documenting the new format and changing the magic number.
+
+ Reviewed-By: Christina Schimpe <christina.schimpe@intel.com>
+ Reviewed-by: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
+ Reviewed-By: Eli Zaretskii <eliz@gnu.org>
+ Approved-By: Guinevere Larsen <guinevere@redhat.com>
+
+2026-07-03 Guinevere Larsen <guinevere@redhat.com>
+
+ gdb/record: extract the PC to record_full_instruction
+ This commit makes it so the PC is not saved as part of the
+ record_full_instruction effects, but rather gets a special location.
+ That is because a couple of commands would really benefit from it being
+ easy to find the PC (especially ones from record-btrace that's haven't
+ been implemented to record-full yet, such as the ones in PR
+ record/18059), while also possibly allowing for one fewer resizing of
+ the effect vector (and saving an entire byte in the process).
+
+ This commit also refactored record_full_read_entry_from_bfd and
+ record_full_write_entry_to_bfd, to make them methods of
+ record_full_reg_entry and record_full_mem_entry, and also creates
+ similar methods for record_full_entry and record_full_instruction.
+ These could be turned into constructors in a future step of
+ c++ification, but it felt like too much change for a single commit.
+
+ Reviewed-by: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
+ Reviewed-By: Christina Schimpe <christina.schimpe@intel.com>
+ Approved-By: Guinevere Larsen <guinevere@redhat.com>
+
+2026-07-03 Guinevere Larsen <guinevere@redhat.com>
+
+ gdb/record: make record_full_history more c++-like
+ This commit moves the function record_full_exec_insn to be a method of
+ the record_full_instruction class.
+
+ Reviewed-by: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
+ Reviewed-By: Christina Schimpe <christina.schimpe@intel.com>
+ Approved-By: Guinevere Larsen <guinevere@redhat.com>
+
+2026-07-03 Guinevere Larsen <guinevere@redhat.com>
+
+ gdb/record: c++ify internal structures of record-full.c
+ This commit adds a constructor, destructor, and some methods to the
+ structures record_full_entry, record_full_reg_entry and
+ record_full_mem_entry. This is a move to disentangle the internal
+ representation of the data and how record-full manipulates it for
+ replaying.
+
+ Along with this change, record_full_entry is changed to use an
+ std::variant, since it was basically doing that already, but now we have
+ the stdlibc++ error checking to make sure we're only accessing elements
+ we're allowed to.
+
+ Reviewed-by: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
+ Reviewed-By: Christina Schimpe <christina.schimpe@intel.com>
+ Approved-By: Guinevere Larsen <guinevere@redhat.com>
+
+2026-07-03 Guinevere Larsen <guinevere@redhat.com>
+
+ gdb/record: remove record_full_insn_num
+ Now that record_full_list uses a deque, we don't need a variable to
+ track the amount of items recorded, so it is just dropped.
+
+ Reviewed-by: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
+ Reviewed-By: Christina Schimpe <christina.schimpe@intel.com>
+ Approved-By: Guinevere Larsen <guinevere@redhat.com>
+
+2026-07-03 Guinevere Larsen <guinevere@redhat.com>
+
+ gdb/record: factor out reading and writing the execution log to corefile
+ Before this commit, the functions to read and write the execution log to
+ a corefile would would have a large section dedicated to handling a
+ single entry from the log. This commit factors out those large sections
+ into their own functions, record_full_read_entry_from_bfd and
+ record_full_write_entry_to_bfd, respectively.
+
+ There should be no functional changes after this commit.
+
+ Reviewed-By: Christina Schimpe <christina.schimpe@intel.com>
+ Approved-By: Guinevere Larsen <guinevere@redhat.com>
+
+2026-07-03 Guinevere Larsen <guinevere@redhat.com>
+
+ gdb/record: Refactor record history
+ This is the first step in a large refactor in how GDB keeps execution
+ history. Rather than using a linked list where multiple entries can
+ describe a single instruction, the history will now be stored in an
+ std::deque, each instruction being one entry in the deque.
+
+ The choice was initially to use an std::vector, but it would become
+ unwieldy because it needs all the memory to be consecutive, which is
+ hard for 200 thousand entries. Deque was picked because it was a nice
+ midpoint between vector (maximum cache cohesion) and linked list
+ (maximum ease of finding space to store more).
+
+ Each instruction in memory will be now one record_full_instruction
+ entry, which for this commit just contains a vector of
+ record_full_entry for the effects of the instruction, and the data that
+ was stored in the record_full_end entry (that is, the instruction number
+ and the signal, if any).
+
+ This change introduced a minimal performance improvement (what's
+ important is that it isn't a degradation) and a reduction in the total
+ memory footprint of roughly 20% if the entire history is used.
+
+ Reviewed-by: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
+ Reviewed-By: Christina Schimpe <christina.schimpe@intel.com>
+ Approved-By: Guinevere Larsen <guinevere@redhat.com>
+
+2026-07-03 Tankut Baris Aktemur <tankutbaris.aktemur@amd.com>
+
+ gdb, amd-dbgapi-target: use pulongest to print id handles
+ In amd-dbgapi-target, there are a number of cases where identifier
+ handles that are obtained from dbgapi are being printed. Those
+ handles are defined to have type uint64_t. Use pulongest when
+ printing them for improved portability.
+
+ In one case, `ptid.tid ()` was being printed for the wave id. Change
+ this to use `wave_id.handle` for consistency with the other cases.
+
+ Approved-by: Lancelot Six <lancelot.six@amd.com> (amdgpu)
+
+2026-07-03 Lancelot SIX <lancelot.six@amd.com>
+
+ gdb/testsuite: fix gdb.rocm/interrupt-twice
+ Since 246aecb1cd1 "gdb/testsuite: make gdb_breakpoint, runto and
+ runto_main use parse_args", gdb_breakpoint arguments changed. The
+ gdb.rocm/interrupt-twice.exp testcase was not updated to call
+ gdb_breakpoint with correct arguments. This due to the new test being
+ reviewed before the gdb_breakpoint landed, but it being pushed after.
+
+ This patch fixes this issue.
+
+ Change-Id: I0204e2c3cc9b704c79ce01386134e13b018593b8
+ Reviewed-By: Tankut Baris Aktemur <TankutBaris.Aktemur@amd.com>
+
+2026-07-03 Jan Beulich <jbeulich@suse.com>
+
+ x86/gas: add missing RegBND to debugging code
+ This must have been overlooked when MPX support was added.
+
+2026-07-03 Luis Machado <luis.machado@amd.com>
+
+ gdb: replace alloca with gdb::unique_xmalloc_ptr in remote-fileio.c
+ remote_fileio_extract_ptr_w_len parsed a debuggee controlled 64 bit
+ length, narrowed it to int with no bounds check, and the value flowed
+ directly into alloca() across RSP File I/O handlers (Fopen, Frename,
+ Funlink, Fstat, Fsystem). A malicious inferior or remote stub could
+ send a crafted packet with a large path length, displacing the stack
+ pointer by up to 2 GiB and potentially crashing the debugger.
+
+ remote_fileio_extract_ptr_w_len now rejects negative lengths, lengths
+ that would overflow the int result (greater than INT_MAX), and zero.
+ An allow_zero_length flag lets the Fsystem handler opt in to the zero
+ length sentinel that signals a NULL cmdline query. All other handlers
+ use the default and are protected without any per call checks. Oversized
+ names are rejected naturally by the underlying syscall with ENAMETOOLONG.
+ All alloca(length) calls have been replaced with
+ gdb::unique_xmalloc_ptr<char>, so an oversized but positive length now
+ fails as a graceful heap allocation error rather than corrupting the
+ stack.
+
+ Add a selftest that exercises various problematic cases.
+
+ Approved-By: Pedro Alves <pedro@palves.net>
+
+2026-07-03 Luis Machado <luis.machado@amd.com>
+
+ gdb/testsuite: deduplicate --offload-arch targets in hcc_amdgpu_targets
+ On systems with multiple identical GPUs, find_amdgpu_devices returns one
+ entry per device, causing hcc_amdgpu_targets to emit redundant
+ --offload-arch flags when compiling HIP test programs (e.g. eight
+ --offload-arch=gfx942 flags on an 8-GPU MI300 system).
+
+ Deduplicate the target list in hcc_amdgpu_targets, preserving order, so
+ each unique architecture appears exactly once regardless of how many
+ physical devices share it. The same deduplication is applied when the
+ list comes from the HCC_AMDGPU_TARGET environment variable. An array
+ is used for the seen-set to give O(1) membership tests.
+
+ Add gdb.rocm/hcc-amdgpu-targets.exp to unit-test the deduplication
+ logic across both the env-var and device-enumeration code paths, without
+ requiring a GPU.
+
+ Approved-by: Lancelot Six <lancelot.six@amd.com>
+
+2026-07-03 Alan Modra <amodra@gmail.com>
+
+ PR 34342 SIGSEGV libctf/ctf-types.c:1603
+ * ctf-open.c (init_static_types_internal): Sanity check variable
+ length record bytes against type section length.
+ (upgrade_types_v1): Likewise. Don't check unused "size" here.
+
+2026-07-03 GDB Administrator <gdbadmin@sourceware.org>
+
+ Automatic date update in version.in
+
+2026-07-02 Tom Tromey <tromey@adacore.com>
+
+ Handle -1 in ptid_t::parse
+ ptid_t::parse fails to correctly handle the -1 return from
+ hex_or_minus_one in the 'p' case. As Mark Wielaard pointed out, it
+ does this check:
+
+ if (hex != ((unsigned_lwp_type) lwp))
+
+ However on 32-bit, this means that it will mishandle (ULONGEST) -1.
+
+ This patch fixes the problem by adding a check for the -1 case.
+
+ I built a -m32 gdb and verified this fix; I'm checking it in.
+
+2026-07-02 Jon Turney <jon.turney@dronecode.org.uk>
+
+ objdump: Fix private header ('-p') import table output for pe-aarch64
+ The private header ('-p') import table output for pe-aarch64 (and
+ probably all other 64-bit arches apart from x86_64) is truncated after the
+ first import.
+
+ The distinction between the conditional branches here should be between
+ PE32 (32-bit) and PE32+ (somewhat confusingly, the 64-bit version of the
+ PE format).
+
+ PE file format specification [1] states under "Import Lookup Table":
+
+ "An import lookup table is an array of 32-bit numbers for PE32 or an
+ array of 64-bit numbers for PE32+."
+
+ [1] https://learn.microsoft.com/en-us/windows/win32/debug/pe-format#import-lookup-table
+
+ 2026-06-19 Jon Turney <jon.turney@dronecode.org.uk>
+
+ * peXXigen.c (pe_print_idata): Fix conditional.
+
+2026-07-02 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
+
+ bfd/readelf: Add core file support for FEAT_S1POE
+ Add support for `NT_ARM_POE` dumps/reads for core files.
+
+2026-07-02 Richard Earnshaw <rearnsha@arm.com>
+
+ aarch64: Adjust architecture version for mpamv2 tests
+ Armv9.3a now permits mpamv2, so lower the version needed for the tests.
+
+2026-07-02 Tom Tromey <tromey@adacore.com>
+
+ Fix ptid_t selftest crash
+ Sam James pointed out that my recent patch to add ptid_t::parse caused
+ a selftest crash.
+
+ At first I couldn't see why this did not crash for me, but then I
+ realized that ptid_t::parse didn't unconditionally initialize '*obuf'.
+ Initializing it to nullptr made this crash reliably.
+
+ The underlying bug is that some code paths in ptid_t::parse don't set
+ obuf on return. This patch fixes the bug by passing 'obuf' down to
+ hex_or_minus_one.
+
+ Since this is straightforward and fixes a new crash, I'm checking it
+ in.
+
+ Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=34340
+
+2026-07-02 Richard Earnshaw <rearnsha@arm.com>
+
+ NEWS: Update for withdrawal of the MPAMv2_VID feature.
+
+ aarch64: Remove +mpamv2 feature option
+ The remaining mpamv2 details only use system registers; so by our
+ conventions we do not use a feature option to enable them. Remove the
+ now redundant +mpamv2 architecture option and adjust the tests
+ accordingly.
+
+ Revert "aarch64: Add FEAT_MPAMv2_VID system registers"
+ This reverts commit 5fc6b09c078532fa4206a350e34d82488b80a5fb.
+
+ Revert "aarch64: Add support for MLBI system instructions"
+ This reverts commit d8e004f124877849c654c0f24c2960970dbc1ee8.
+
+ aarch64: remove MLBI from sys-rt-alias test.
+
+2026-07-02 Richard Earnshaw <rearnsha@arm.com>
+
+ aarch64: warn if the TME feature is used during assembly.
+ Arm has obsoleted the unimplemented TME feature. Warn if instructions
+ from this feature are encountered.
+
+ Also tweak warn_unpredictable_ldst to use const more often, since the
+ arguments are the same as for the new warn_deprecated function.
+
+2026-07-02 Richard Earnshaw <rearnsha@arm.com>
+
+ aarch64: Remove a stray comment from opcode/aarch64.h
+ When flag bit 28 was removed in an earlier patch, the comment describing
+ it was left behind. This just cleans that up.
+
+2026-07-02 Clément Chigot <chigot@adacore.com>
+
+ ld/testsuite: add support for remote testing in ld-cdtest
+ This converts the existing to code to use "remote_load" allowing
+ execution on both native and remote targets.
+
+ The "diff" between the output and the expected result has been
+ transformed to the usual regexp_diff. The previous could have been
+ transformed into `remote_exec build diff` but tends to be fickled with
+ new lines.
+
+2026-07-02 Alan Modra <amodra@gmail.com>
+
+ Re: x86: Disable AMX-TF32 by default
+ Regenerate opcodes/i386-init.h, which was listed in the changelog but
+ not committed.
+
+2026-07-02 Alan Modra <amodra@gmail.com>
+
+ PR 34327 More out of bounds accesses in reloc special functions
+ I don't claim to have caught all places where reloc special functions
+ don't sanity check input, but this should be most of them. Hopefully
+ this does not expose odd reloc howto entries like the mmix one in the
+ previous patch.
+
+ * coff-arm.c (aoutarm_fix_pcrel_26): Sanity check reloc offset.
+ Remove some unnecessary casts.
+ (coff_thumb_pcrel_common): Likewise.
+ * coff-mips.c (mips_generic_reloc): Remove unnecessary casts.
+ (mips_refhi_reloc): Likewise.
+ (mips_gprel_reloc): Likewise. Use bfd_reloc_offset_in_range.
+ * cpu-ns32k.c (do_ns32k_reloc): Likewise.
+ * elf32-m68hc1x.c (m68hc11_elf_special_reloc): Likewise. Don't
+ abort, return notsupported instead.
+ * elf32-pj.c (pj_elf_reloc): Sanity check reloc offset.
+ * elf32-pru.c (pru_elf32_do_s10_pcrel_relocate): Update reloc
+ offset sanity check.
+ (pru_elf32_do_ldi32_relocate): Likewise.
+ * elf32-s390.c (s390_elf_ldisp_reloc): Use bfd_reloc_offset_in_range.
+ Remove unnecessary casts.
+ * elf32-score7.c (score_elf_got_lo16_reloc): Remove redundant old
+ reloc offset sanity check.
+ * elf32-sh.c (sh_elf_reloc): Use bfd_reloc_offset_in_range.
+ * elf32-v850.c (v850_elf_reloc): Likewise.
+
+2026-07-02 Alan Modra <amodra@gmail.com>
+
+ PR 34327 Out of bounds accesses in reloc special functions.
+ As per the PR, s12z lacked any reloc offset sanity checking, the
+ others all just checked that the offset started within the section
+ rather than checking the field was contained in the section.
+
+ Using the proper check for mmix exposed a problem in the howto table,
+ present since the initial mmix commit. The R_MMIX_BASE_PLUS_OFFSET
+ field is actually two bytes, located at the reloc address. Making it
+ an eight byte field is just wrong, as doing that indicates the field
+ is at the reloc address plus six bytes for a big-endian target.
+ Presumably this was done for overlow reporting, which is properly done
+ by appropriately setting complain_on_overflow.
+
+ * elf32-d30v.c (bfd_elf_d30v_reloc, bfd_elf_d30v_reloc_21): Use
+ bfd_reloc_offset_in_range
+ * elf32-s12z.c (opru18_reloc): Likewise.
+ * elf32-spu.c (spu_elf_rel9): Likewise.
+ * elf32-xstormy16.c (xstormy16_elf_24_reloc): Likewise.
+ * elf32-visium.c (visium_elf_howto_parity_reloc): Likewise.
+ Remove unnecessary casts too.
+ * elf64-s390.c (s390_elf_ldisp_reloc): Likewise.
+ * elfxx-sparc.c (init_insn_reloc): Likewise.
+ * elf64-mmix.c (mmix_elf_reloc): Likewise. Remove unnecessary
+ variable too.
+ (elf_mmix_howto_table[R_MMIX_BASE_PLUS_OFFSET]): Correct size,
+ bitsize and complain_on_overflow.
+
+2026-07-02 Alan Modra <amodra@gmail.com>
+
+ PR 34165 aarch64 assertion fail and segv
+ * elfnn-aarch64.c (dtpoff_base, tpoff_base): Don't assert that
+ tls_sec is non-NULL, return zero instead.
+
+2026-07-02 Haochen Jiang <haochen.jiang@intel.com>
+
+ x86: Disable AMX-TF32 by default
+ AMX-TF32 got depublished in ISE062. Just like AMX-TRANSPOSE, we
+ will keep the AMX-TF32 support for now in case there are x86 vendors
+ want to utilize the feature. AMX-TF32 will not show up on any
+ Intel/AMD hardware. Also in foreseeable future, no hardware will
+ support AMX-TF32, we will disable it by default. For testcases,
+ we will simply add .arch .amx_tf32 to keep the original test
+ intuition.
+
+ gas/ChangeLog:
+
+ * testsuite/gas/i386/x86-64-amx-tf32.s: Add .amx_tf32.
+ * testsuite/gas/i386/x86-64-amx-tf32-inval.s: Ditto.
+ * testsuite/gas/i386/x86-64-amx-transpose.s: Ditto.
+ * testsuite/gas/i386/x86-64-amx-transpose-inval.s: Ditto.
+ * testsuite/gas/i386/x86-64-amx-tf32-inval.l: Adjust line
+ number.
+ * testsuite/gas/i386/x86-64-amx-transpose-inval.l: Ditto.
+
+ opcodes/ChangeLog:
+
+ * i386-gen.c: Disable AMX-TF32 by default.
+ * i386-init.h: Regenerated.
+
+2026-07-02 GDB Administrator <gdbadmin@sourceware.org>
+
+ Automatic date update in version.in
+
+2026-07-02 H.J. Lu <hjl.tools@gmail.com>
+
+ readelf: Avoid may be used uninitialized warning from GCC 14
+ GCC 14 fails to recognize that rel_entsz and entsz_name are unused when
+ process_relocs returns early for error:
+
+ .../binutils/readelf.c:10127:18: error: ‘rel_entsz’ may be used uninitialized [-Werror=maybe-uninitialized]
+ 10127 | if (rel_entsz == 0)
+ | ^
+ ...
+ .../binutils/readelf.c:10129:19: error: ‘entsz_name’ may be used uninitialized [-Werror=maybe-uninitialized]
+ 10129 | printf (_("<missing or corrupt dynamic tag: %s>\n"),
+ | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ 10130 | entsz_name);
+
+ Clear them before returning error. Also replace reltype_unknown with
+ default since GCC 14 fails to see that reltype_unknown is the only
+ unhandled value for relocation_type enum.
+
+ PR binutils/34324
+ * readelf.c (process_relocs): Clear rel_entsz and entsz_name
+ before returning error on missing DT_REL and DT_RELA dynamic
+ tags.
+
+2026-07-01 H.J. Lu <hjl.tools@gmail.com>
+
+ readelf: Check missing DT_REL and DT_RELA dynamic tags
+ PR binutils/34324
+ * readelf.c (process_relocs): Return error on missing DT_REL and
+ DT_RELA dynamic tags.
+
+2026-07-01 Tom Tromey <tromey@adacore.com>
+
+ Do not write negative PID or TID in remote protocol
+ Currently both gdb and gdbserver can write a negative number for the
+ PID or TID. However, the only negative value that really makes sense
+ is the special case of "-1" -- in other cases if the PID or TID has
+ the high bit set, it should still be written as a positive number.
+
+ This patch attempts to fix the bug.
+
+ v2 of this patch combines the implementations and moves them to
+ gdbsupport. I tried making these standalone functions in rsp-low.cc,
+ but that runs afoul of libipa. So, I made them methods of ptid_t.
+
+ The new unit tests pointed out that round-tripping a sign-extended
+ number didn't really work, because the checks were done via ULONGEST.
+ It's kind of unfortunate that the PID and LWP are host-dependent
+ types. This should probably be fixed, but I haven't done so here.
+ Meanwhile I changed the checks to use the corresponding unsigned type.
+
+ v1 is here
+
+ https://inbox.sourceware.org/gdb-patches/20260311202152.2704410-1-tromey@adacore.com/
+
+ Regression tested on x86-64 Fedora 43.
+
+ Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=25111
+ Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=33979
+ Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=33983
+
+2026-07-01 Alan Modra <amodra@gmail.com>
+
+ libiberty d_compact_number signed integer overflow
+ https://lists.gnu.org/archive/html/bug-binutils/2026-06/msg00189.html
+ Fix this by doing the addition in unsigned arithmetic.
+
+2026-07-01 GDB Administrator <gdbadmin@sourceware.org>
+
+ Automatic date update in version.in
+
+2026-07-01 Peter Damianov <peter0x44@disroot.org>
+
+ ld/testsuite: Add comprehensive PE COFF weak external tests
+ Add tests covering the full matrix of weak/strong symbol interactions
+ for PE COFF weak externals, based on testcases by Martin Storsjo.
+ The archive test covers PE weak externals whose public name is backed
+ by a real fallback definition, and ensures weak declarations with the
+ null fallback are not advertised as archive providers.
+
+ ld/testsuite/
+
+ * ld-pe/pe-compile.exp (weak_ext_test): New proc. Compiles
+ source files, links via gcc, and runs natively if possible.
+ (weak_ext_archive_test): New proc.
+ Add tests: normal, weak-undef, weak-defined,
+ weak-decl-weak-def, strong-undef-weak-def-archive, weak-use,
+ weak-override, weak-duplicate, weak-def-override, weak-def-use.
+ * ld-pe/weak-ext-main.c: New file.
+ * ld-pe/weak-ext-main-weak.c: New file.
+ * ld-pe/weak-ext-main-weak-def.c: New file.
+ * ld-pe/weak-ext-add2.c: New file.
+ * ld-pe/weak-ext-add1-weak-chained.c: New file.
+ * ld-pe/weak-ext-dummy.c: New file.
+ * ld-pe/weak-ext-expected1.c: New file.
+ * ld-pe/weak-ext-expected3.c: New file.
+ * ld-pe/weak-ext-expected5.c: New file.
+ * ld-pe/weak-ext-expected3-add1-weak.c: New file.
+
+2026-07-01 Peter Damianov <peter0x44@disroot.org>
+
+ bfd: Handle PE weak externals with real fallbacks in archives
+ PE weak externals are canonicalized as undefined BFD symbols, even
+ when their auxiliary entry names a real fallback definition in the same
+ object. Archive map generation therefore skipped the public weak name,
+ so a strong undefined reference to that name could not extract the
+ archive member.
+
+ Include such PE weak externals in the archive map, but only when the
+ fallback is a real definition rather than the absolute-zero null symbol
+ used for weak declarations with no fallback. Also avoid extracting an
+ archive member again during repeated archive searches once the weak
+ external resolves through a defined fallback.
+
+ Fixes: https://gcc.gnu.org/PR124263
+
+ bfd/
+
+ * archive.c: Include coff-bfd.h.
+ (_bfd_compute_and_push_armap): Include PE weak externals in
+ the archive map when their fallback is a real definition.
+ * coff-bfd.c (bfd_coff_pe_weak_external_has_real_fallback): New
+ function.
+ * coff-bfd.h (bfd_coff_pe_weak_external_has_real_fallback):
+ Declare.
+ * cofflink.c (coff_link_hash_pe_weak_external_has_real_fallback):
+ New function.
+ (coff_link_check_archive_element): Avoid extracting an archive
+ member again for a PE weak external whose real fallback is
+ already defined.
+
+2026-07-01 Peter Damianov <peter0x44@disroot.org>
+
+ PE-COFF: Prefer weak external with defined fallback over null fallback
+ When two PE COFF weak externals for the same symbol are linked (both
+ C_NT_WEAK with aux records), the generic linker takes no action on the
+ second one (NOACT: weak undef meets existing weak undef). This means
+ the first file's fallback alias always wins regardless of whether it
+ points to a real definition or to NULL.
+
+ This causes a problem when a weak declaration (fallback = NULL,
+ i.e. "resolve to NULL if nothing provides it") is linked before a
+ weak definition (fallback = actual function body). The symbol resolves
+ to address 0 at runtime, causing a crash when called.
+
+ Fix this by comparing the fallback targets when two weak externals
+ meet: if the incoming weak external's fallback resolves to a defined
+ symbol and the existing one does not (or points to NULL),
+ update the aux record to use the better fallback.
+
+ This matches the behavior of lld after:
+ https://github.com/llvm/llvm-project/commit/7ca5698b4c3698d06065e0941df7f23d72913d23
+
+ bfd/
+ * cofflink.c (coff_link_add_symbols): When two PE COFF weak
+ externals meet, prefer the one whose fallback alias resolves
+ to a defined symbol.
+
+2026-07-01 Peter Damianov <peter0x44@disroot.org>
+
+ PE-COFF: Fix weak external symbol resolution when strong undef is seen first
+ When linking PE-COFF objects, a weak external symbol (C_NT_WEAK with an
+ aux record specifying a fallback alias) may fail to resolve if a strong
+ undefined reference to the same symbol is encountered before the weak
+ definition. This causes "undefined reference" errors for symbols like
+ operator new or personality routines that GCC emits as weak externals
+ with a fallback to a default implementation.
+
+ There are two problems:
+
+ 1. In coff_link_add_symbols, when the generic linker resolves a weak
+ undefined against an existing strong undefined (NOACT in the action
+ table), the COFF-specific symbol_class and aux record were not stored
+ because the existing hash entry already had non-null class/type from
+ the first (strong) object file.
+
+ 2. In _bfd_coff_generic_relocate_section, the weak alias fallback only
+ triggered for bfd_link_hash_undefweak symbols. When a strong undef
+ is seen first, the hash type stays bfd_link_hash_undefined (the
+ generic linker does not downgrade it), so the fallback was skipped.
+
+ Fix by extending the condition in coff_link_add_symbols to also update
+ symbol_class and aux when the incoming symbol is a PE weak external
+ with aux and the existing hash is still undefined. Also extend the
+ relocation handler to resolve the weak alias fallback for
+ bfd_link_hash_undefined symbols that carry C_NT_WEAK class and have
+ an aux record.
+
+ bfd/
+ * cofflink.c (coff_link_add_symbols): Also store symbol_class
+ and aux record when a PE weak external with aux meets an
+ existing undefined hash entry.
+ (_bfd_coff_generic_relocate_section): Also resolve weak alias
+ fallback for undefined symbols with C_NT_WEAK class and aux.
+
+2026-06-30 Jiawei <jiawei@iscas.ac.cn>
+
+ RISC-V: Fix zvdota altfmt disassemble format issue
+ Fix-up vtype altfmt disassembly extension check.
+
+ Only print the altfmt vtype names when the object advertises one of the
+ extensions that defines that encoding, or when disassembling with all
+ extensions enabled.
+
+ Validated with:
+ make check RUNTEST=... RUNTESTFLAGS="riscv.exp"
+
+ Result:
+ PASS: gas/riscv/vector-insns
+ PASS: gas/riscv/zvdota
+ # of expected passes: 360
+
+ gas/ChangeLog:
+
+ * testsuite/gas/riscv/zvdota.d: Fix format.
+
+ opcodes/ChangeLog:
+
+ * riscv-dis.c (riscv_vtype_altfmt_supported): Add ext check.
+ (print_insn_args): Use altfmt check.
+
+2026-06-30 Jiawei <jiawei@iscas.ac.cn>
+
+ RISC-V: Add Zvbdota extension support
+ This patch supports the RISC-V Zvbdota family of batched dot-product
+ extensions [1].
+
+ Compared to the non-batched Zvdota family, Zvbdota computes up to eight
+ dot products at a time. These instructions use an EMUL=8 `vs2` vector
+ register group and a scaled-by-8 `ci` immediate encoded in `vs2[2:0]`.
+ This patch adds assembler/disassembler support for those additional
+ operand constraints.
+
+ The Zvbdota extension family includes the following extensions:
+
+ * Zvqwbdota8i: batched dot product of 8-bit integers with 32-bit
+ accumulation.
+ * Zvqwbdota16i: batched dot product of 16-bit integers with 64-bit
+ accumulation.
+ * Zvfwbdota16bf: batched dot product of bfloat16 floating-point numbers
+ with 32-bit accumulation.
+ * Zvfqwbdota8f: batched dot product of 8-bit floating-point numbers with
+ 32-bit accumulation.
+ * Zvfbdota32f: batched dot product of 32-bit single-precision
+ floating-point numbers with 32-bit accumulation.
+
+ [1] https://github.com/riscv/riscv-isa-manual/blob/zvbdot/src/zvdota.adoc
+
+ bfd/ChangeLog:
+
+ * elfxx-riscv.c (riscv_implicit_subsets): New implies.
+ (riscv_supported_std_z_ext): New extensions.
+ (riscv_multi_subset_supports): Ditto.
+ (riscv_multi_subset_supports_ext): Ditto.
+
+ gas/ChangeLog:
+
+ * NEWS: Add zvqwbdota8i, zvqwbdota16i, zvfwbdota16bf,
+ zvfqwbdota8f and zvfbdota32f extensions.
+ * config/tc-riscv.c (validate_riscv_insn): Add Zvbdota operand
+ type 'q' and 'r' bits validation.
+ (riscv_vtype_altfmt_supported): Add Zvbdota extensions.
+ (my_getVsetvliExpression): Update altfmt error message.
+ (riscv_ip): Add 'q' operand for VS2 EMUL=8 alignment check
+ and 'r' operand for ci immediate.
+ * testsuite/gas/riscv/march-help.l: Ditto.
+ * testsuite/gas/riscv/zvbdota.d: New test.
+ * testsuite/gas/riscv/zvbdota.s: Ditto.
+ * testsuite/gas/riscv/zvbdota-operands-fail.d: Ditto.
+ * testsuite/gas/riscv/zvbdota-operands-fail.l: Ditto.
+ * testsuite/gas/riscv/zvbdota-operands-fail.s: Ditto.
+ * testsuite/gas/riscv/zvbdota-zvqwbdota16i.d: Ditto.
+ * testsuite/gas/riscv/zvbdota-zvqwbdota16i.s: Ditto.
+
+ include/ChangeLog:
+
+ * opcode/riscv-opc.h (MATCH_VQWBDOTAU_VV, MASK_VQWBDOTAU_VV):
+ New encoding.
+ (MATCH_VQWBDOTAS_VV, MASK_VQWBDOTAS_VV): Ditto.
+ (MATCH_VFWBDOTA_VV, MASK_VFWBDOTA_VV): Ditto.
+ (MATCH_VFQWBDOTA_VV, MASK_VFQWBDOTA_VV): Ditto.
+ (MATCH_VFQWBDOTA_ALT_VV, MASK_VFQWBDOTA_ALT_VV): Ditto.
+ (MATCH_VFBDOTA_VV, MASK_VFBDOTA_VV): Ditto.
+ (DECLARE_INSN): New declarations.
+ * opcode/riscv.h (enum riscv_insn_class): New extension classes.
+
+ opcodes/ChangeLog:
+
+ * riscv-dis.c (print_insn_args): Add 'q' and 'r' operand types
+ for Zvbdota.
+ * riscv-opc.c (riscv_opcodes): New instructions.
+
+2026-06-30 Jiawei <jiawei@iscas.ac.cn>
+
+ RISC-V: Add Zvdota extension classes
+ Zvfqwdota8f: dot product of 8-bit floating-point numbers with 32-bit accumulation.
+
+ Zvdota also uses the vtype alternative format bit, altfmt, which is bit 8 of the vtype CSR. This patch adds symbolic e8alt and e16alt vsew constants for vsetvli/vsetivli so that assembly code can select the alternative element formats required by these dot-product instructions.
+
+ [1] https://github.com/riscv/riscv-isa-manual/blob/zvbdot/src/zvdota.adoc
+
+ bfd/ChangeLog:
+
+ * elfxx-riscv.c (riscv_implicit_subsets): New implies.
+ (riscv_supported_std_z_ext): New extensions.
+ (riscv_multi_subset_supports): Ditto.
+ (riscv_multi_subset_supports_ext): Ditto.
+
+ gas/ChangeLog:
+
+ * NEWS: Add zvqwdota8i, zvqwdota16i, zvfwdota16bf and
+ zvfqwdota8f extensions.
+ * config/tc-riscv.c (riscv_vsew_altfmt): New vsew altfmt
+ constants array for e8alt and e16alt.
+ (riscv_vtype_altfmt_supported): New function.
+ (my_getVsetvliExpression): Ditto.
+ * testsuite/gas/riscv/march-help.l: New test.
+ * testsuite/gas/riscv/vector-vtype-altfmt.d: Ditto.
+ * testsuite/gas/riscv/vector-vtype-altfmt.s: Ditto.
+ * testsuite/gas/riscv/zvdota.d: Ditto.
+ * testsuite/gas/riscv/zvdota.s: Ditto.
+
+ include/ChangeLog:
+
+ * opcode/riscv-opc.h (MATCH_VQWDOTAU_VV, MASK_VQWDOTAU_VV): New encoding.
+ (MATCH_VQWDOTAS_VV, MASK_VQWDOTAS_VV): Ditto.
+ (MATCH_VFWDOTA_VV, MASK_VFWDOTA_VV): Ditto.
+ (MATCH_VFQWDOTA_VV, MASK_VFQWDOTA_VV): Ditto.
+ (MATCH_VFQWDOTA_ALT_VV, MASK_VFQWDOTA_ALT_VV): Ditto.
+ (DECLARE_INSN): New declarations.
+ * opcode/riscv.h (OP_MASK_VTYPE_ALTFMT, OP_SH_VTYPE_ALTFMT): New vtype altfmt.
+ (enum riscv_insn_class): New extension classes.
+
+ opcodes/ChangeLog:
+
+ * riscv-dis.c (print_insn_args): Add altfmt support.
+ * riscv-opc.c (riscv_opcodes): New instructions.
+
+2026-06-30 H.J. Lu <hjl.tools@gmail.com>
+
+ readelf: Also set do_got_section_contents to false
+ Also set do_got_section_contents to false if section headers are failed
+ to load.
+
+ PR binutils/34323
+ * readelf.c (process_object): Also set do_got_section_contents.
+
+2026-06-30 Alan Modra <amodra@gmail.com>
+
+ ld testsuite alpha_ld_flags
+ This is how alpha can use -Ttext-segment on just those tests that need
+ it. And since the way run_dump_test uses $opts(ld) allows tcl procs to
+ be embedded, there is no need to specially expand [big_or_little_endian].
+
+ binutils/
+ * testsuite/lib/binutils-common.exp (run_dump_test <opts(ld)>): No
+ need to handle big_or_little_endian specially.
+ ld/
+ * testsuite/ld-elf/elf.exp (alpha_ld_flags): New proc.
+ (LDFLAGS): Don't set -Ttext-segment for alpha globally.
+ * testsuite/ld-elf/compress1a.d: Add alpha_ld_flags.
+ * testsuite/ld-elf/compressed1a.d: Likewise.
+ * testsuite/ld-elf/eh5.d: Likewise.
+
+2026-06-30 GDB Administrator <gdbadmin@sourceware.org>
+
+ Automatic date update in version.in
+
+2026-06-30 H.J. Lu <hjl.tools@gmail.com>
+
+ elf: Set image base address to the maximum page size
+ When generating Position Dependent Executable for ELF with the maximum
+ page size set on command-line, set the default image base address to the
+ maximum page size to avoid segfault if it is lower than the maximum page
+ size and issue an warning if the image base address set on command-line
+ is lower than the maximum page size.
+
+ PR ld/34184
+ * ldexp.c (fold_binary): Set the default image base address to
+ the maximum page size for ELF PDE output if it is lower than
+ the maximum page size set on command-line and issue an warning
+ if the image base address set on command-line is lower than the
+ maximum page size.
+ * testsuite/ld-elf/elf.exp: Add ld/34184 tests for PDE, PIE
+ static PDE and static PIE.
+ * testsuite/ld-elf/pr34184.c: New file.
+ * testsuite/ld-elf/textaddr3.d: Change -Ttext-segment address
+ to 0x200100 so that it > the maximum page size.
+ * testsuite/ld-elf/textaddr5.d: Likewise.
+ * testsuite/ld-elf/textaddr8.d: New test.
+ * testsuite/ld-elf/textaddr9.d: Likewise.
+ * testsuite/ld-elf/textaddr10.d: Likewise.
+
+2026-06-29 Oleg Tolmatcev <oleg.tolmatcev@gmail.com>
+
+ PE/COFF: auto-promote oversized objects to bigobj
+ PE/COFF object files use 16-bit section numbers in normal symbols.
+ When an object grows past that limit, current BFD already rejects it with
+ a "too many sections" / "file too big" error.
+
+ BFD already has PE bigobj targets for the backends that support them, but
+ oversized PE/COFF output still requires selecting bigobj explicitly.
+
+ Teach coff_compute_section_file_positions to switch PE/COFF output to the
+ corresponding bigobj target when the normal section-number limit is
+ exceeded. This preserves the existing hard error for targets without
+ bigobj support, but lets supported PE targets transparently emit a valid
+ bigobj object instead of requiring manual selection.
+
+ bfd/
+ * coffcode.h (coff_compute_section_file_positions): Auto-promote
+ oversized PE/COFF objects to the bigobj target.
+
+ gas/
+ * testsuite/gas/pe/big-obj-auto.d: New test.
+ * testsuite/gas/pe/big-obj-auto.s: New test.
+ * testsuite/gas/pe/pe.exp: Run big-obj-auto.
+
+2026-06-29 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
+
+ bfd: Always use CP_ACP=1 on Solaris [PR11280]
+ bfd/configure.host defines CP_ACP=1 on Solaris 11 as a workaround for
+ the lack the MS-ANSI codepage in Solaris libc iconv(3C). However, the
+ issue isn't restricted to some OpenSolaris build as the comment
+ suggests, but present on Solaris in general as can be seen in the iconv -l
+ output:
+
+ On both Solaris 10 and 11.4, one gets
+
+ CP1252 (1252, ANSI-1252, WINDOWS-1252),
+
+ unlike GNU iconv which lists
+
+ CP1252 MS-ANSI WINDOWS-1252
+
+ Therefore, this patch applies the patch on all Solaris versions.
+
+ Tested on {amd64,i386}-pc-solaris2.11 and sparc{v9,}-sun-solaris2.11.
+
+ 2026-06-28 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
+
+ bfd:
+ PR binutils/11280
+ * configure.host (HDEFINES): Always define CP_ACP=1 on Solaris.
+
+2026-06-29 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
+
+ Remove 32-bit-only Solaris configurations
+ After the removal of all Solaris configurations but Solaris 10/11
+ (*-*-solaris2.1[01]), the 32-bit-only configurations can no longer be
+ matched. This patch removes them.
+
+ Tested on {amd64,i386}-pc-solaris2.11 and sparc{v9,}-sun-solaris2.11.
+
+ 2026-06-28 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
+
+ bfd:
+ * config.bfd <i[3-7]86-*-solaris*>: Remove.
+ <sparc*-*-solaris*>: Likewise.
+
+ ld:
+ * configure.tgt <i[3-7]86-*-solaris*>: Remove.
+ <sparc*-*-solaris*>: Likewise.
+
+2026-06-29 Mark Zhuang <mark.zhuang@spacemit.com>
+
+ RISC-V: Fix build with clang and gcc prior to gcc11
+ A label followed by a declaration is a C23 extension.
+ Add braces to fix it.
+
+2026-06-29 GDB Administrator <gdbadmin@sourceware.org>
+
+ Automatic date update in version.in
+
+2026-06-28 H.J. Lu <hjl.tools@gmail.com>
+
+ ld-elf/linux-x86.exp: Remove $options in readelf log
+ Remove $options in readelf log since it isn't passed to readelf.
+
+ * testsuite/ld-elf/linux-x86.exp (elfedit_test): Remove $options
+ in readelf log.
+
+2026-06-28 Georg-Johann Lay <avr@gjlay.de[...]
[diff truncated at 100000 bytes]
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