[binutils-gdb] RISC-V: EEW64 checking

[Jan Beulich]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=790c615e49d7104abcbd4397e6ca1331181d900b

commit 790c615e49d7104abcbd4397e6ca1331181d900b
Author: Jan Beulich <jbeulich@suse.com>
Date:   Fri Jul 24 08:15:18 2026 +0200

    RISC-V: EEW64 checking
    
    Like the assembler, the disassembler should also use the INSN_V_EEW64
    flag. Respectively marked insns shouldn't be disassembled normally when
    Zve64x isn't enabled.
    
    While there also drop the redundant Zve32x check from gas: All affected
    insns are INSN_CLASS_V, which means Zve32x was already checked to be
    enabled (both V and Zve64x imply Zve32x).

Diff:
---
 gas/config/tc-riscv.c           |  5 ++---
 gas/testsuite/gas/riscv/eew64.d | 13 +++++++++++++
 gas/testsuite/gas/riscv/eew64.s | 12 ++++++++++++
 opcodes/riscv-dis.c             | 14 ++++++++++----
 4 files changed, 37 insertions(+), 7 deletions(-)

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 946bc4a0227..b7eca324bc3 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -3040,10 +3040,9 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 		      insn_with_csr = false;
 		    }
 
-		  /* The (segmant) load and store with EEW 64 cannot be used
+		  /* The (segment) load and store with EEW 64 cannot be used
 		     when zve32x is enabled.  */
-		  if (ip->insn_mo->pinfo & INSN_V_EEW64
-		      && riscv_subset_supports (&riscv_rps_as, "zve32x")
+		  if ((ip->insn_mo->pinfo & INSN_V_EEW64)
 		      && !riscv_subset_supports (&riscv_rps_as, "zve64x"))
 		    {
 		      error.msg = _("illegal opcode for zve32x");
diff --git a/gas/testsuite/gas/riscv/eew64.d b/gas/testsuite/gas/riscv/eew64.d
new file mode 100644
index 00000000000..34a4c12bdfa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/eew64.d
@@ -0,0 +1,13 @@
+#as: -march=rv32i
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <eew32>:
+[ 	]+0:[ 	]+020ff007[ 	]+\.insn[ 	]+4, ?0x020ff007
+
+0+004 <eew64>:
+[ 	]+4:[ 	]+020ff007[ 	]+vle64\.v[ 	]+v0,\(t6\)
+#pass
diff --git a/gas/testsuite/gas/riscv/eew64.s b/gas/testsuite/gas/riscv/eew64.s
new file mode 100644
index 00000000000..d3f0203938c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/eew64.s
@@ -0,0 +1,12 @@
+	.option arch, rv32i
+	.option arch, +zve32x
+
+eew32:
+	# vle64.v v0, (x31)
+	.insn 4, 0x020ff007
+
+	.option arch, rv32i
+	.option arch, +zve64x
+
+eew64:
+	vle64.v	v0, (x31)
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index e5a9e66f2e2..73e19baf684 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -1128,10 +1128,16 @@ riscv_disassemble_insn (bfd_vma memaddr,
 	      && (op->xlen_requirement != pd->xlen))
 	    continue;
 	  /* Is this instruction supported by the current architecture?  */
-	  if (!pd->all_ext
-	      && !riscv_multi_subset_supports (&pd->riscv_rps_dis,
-					       op->insn_class))
-	    continue;
+	  if (!pd->all_ext)
+	    {
+	      if (!riscv_multi_subset_supports (&pd->riscv_rps_dis,
+						op->insn_class))
+		continue;
+
+ 	      if ((op->pinfo & INSN_V_EEW64)
+		  && !riscv_subset_supports (&pd->riscv_rps_dis, "zve64x"))
+		continue;
+	    }
 
 	  /* It's a match.  */
 	  (*info->fprintf_styled_func) (info->stream, dis_style_mnemonic,