[binutils-gdb] aarch64: Add support for FEAT_SME_FA64

[Alice Carlotti]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=d708c86adccb169dd8bf5c7f4d73d7cab238d965

commit d708c86adccb169dd8bf5c7f4d73d7cab238d965
Author: Alice Carlotti <alice.carlotti@arm.com>
Date:   Thu Jul 9 18:27:43 2026 +0100

    aarch64: Add support for FEAT_SME_FA64
    
    Add "+sme-f64" to the list of architecture extensions.  This has already
    been supported in LLVM for several years.
    
    We don't need to update the feature requirements for any opcodes,
    because FEAT_SME_FA64 only enables instructions that were already
    available in non-streaming mode, and the feature checks don't know what
    mode an instruction will be run under.

Diff:
---
 gas/config/tc-aarch64.c         | 1 +
 gas/doc/c-aarch64.texi          | 2 ++
 gas/testsuite/gas/aarch64/sme.d | 1 +
 include/opcode/aarch64.h        | 2 ++
 4 files changed, 6 insertions(+)

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index dddaa615ab8..cb1613b3bbe 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -11154,6 +11154,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
   {"sve-b16mm",		AARCH64_FEATURE (SVE_B16MM), AARCH64_FEATURE (SVE)},
   {"mtetc",		AARCH64_FEATURE (MTETC), AARCH64_FEATURE (MEMTAG)},
   {"tlbid",		AARCH64_FEATURE (TLBID), AARCH64_NO_FEATURES},
+  {"sme-fa64",		AARCH64_FEATURE (SME_FA64), AARCH64_FEATURES (2, SVE2, SME)},
   {NULL,		AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
 };
 
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 62744d36aa2..6a9fa2f98f3 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -324,6 +324,8 @@ automatically cause those extensions to be disabled.
  @tab Enable the SME2 F16F16 Extension.
 @item @code{sme-f64f64} @tab @code{sme}
  @tab Enable SME F64F64 Extension.
+@item @code{sme-fa64} @tab @code{sme}, @code{sve2}
+ @tab Enable SME F64F64 Extension.
 @item @code{sme-i16i64} @tab @code{sme}
  @tab Enable SME I16I64 Extension.
 @item @code{sme-lutv2} @tab
diff --git a/gas/testsuite/gas/aarch64/sme.d b/gas/testsuite/gas/aarch64/sme.d
index 9317163790a..68f4baf2189 100644
--- a/gas/testsuite/gas/aarch64/sme.d
+++ b/gas/testsuite/gas/aarch64/sme.d
@@ -1,5 +1,6 @@
 #name: SME extension
 #as: -march=armv8-a+sme
+#as: -march=armv8-a+sme-fa64
 #objdump: -dr
 
 .*:     file format .*
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 81bdf337786..e07cbb35a3c 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -288,6 +288,8 @@ enum aarch64_feature_bit {
   AARCH64_FEATURE_MTETC,
   /* TLBI Domains.  */
   AARCH64_FEATURE_TLBID,
+  /* SME_FA64.  */
+  AARCH64_FEATURE_SME_FA64,
 
   /* Virtual features.  These are used to gate instructions that are enabled
      by either of two (or more) sets of command line flags.  */