[binutils-gdb] aarch64: Add support for FEAT_TLBID feature
Alice Carlotti
acarlotti@sourceware.org
Sat Jan 24 07:17:44 GMT 2026
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=1d0e527aa62583706b296db0e3583a2ce6c67340
commit 1d0e527aa62583706b296db0e3583a2ce6c67340
Author: Srinath Parvathaneni <srinath.parvathaneni@arm.com>
Date: Fri Jan 23 22:25:27 2026 +0000
aarch64: Add support for FEAT_TLBID feature
TLBI Domains feature changes TLBI and TLBIP system instructions.
For the TLBI instruction with optional register argument
<Rt> == 0b1111, with FEAT_TLBID enabled they are permitted to
have an Rt value which is not 0b11111 and this is allowed for
all the TLBI instructions with a <type> of ALLE1*, ALLE2*,
VMALL*, VMALLS12* or VMALLWS2* and a <shareability> of IS or OS.
This patch add support for FEAT_TLBID feature, which is enabled
by new +tlbid option.
Diff:
---
gas/config/tc-aarch64.c | 12 ++++-
gas/doc/c-aarch64.texi | 2 +
gas/testsuite/gas/aarch64/tlbid-1.d | 32 ++++++++++++
gas/testsuite/gas/aarch64/tlbid-1.s | 28 +++++++++++
gas/testsuite/gas/aarch64/tlbid-invalid-1.d | 3 ++
gas/testsuite/gas/aarch64/tlbid-invalid-1.l | 43 ++++++++++++++++
gas/testsuite/gas/aarch64/tlbid-invalid-1.s | 20 ++++++++
include/opcode/aarch64.h | 3 ++
opcodes/aarch64-dis.c | 7 ++-
opcodes/aarch64-opc.c | 78 +++++++++++++++++++----------
opcodes/aarch64-opc.h | 3 ++
11 files changed, 202 insertions(+), 29 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index e3accf0acb5..52e72fad1b1 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -5075,6 +5075,7 @@ parse_sys_ins_reg (char **str, htab_t sys_ins_regs, bool sysreg128_p)
char *p, *q;
char buf[AARCH64_MAX_SYSREG_NAME_LEN];
const aarch64_sys_ins_reg *o;
+ aarch64_feature_set set;
p = buf;
for (q = *str; ISALNUM (*q) || *q == '_'; q++)
@@ -5092,9 +5093,17 @@ parse_sys_ins_reg (char **str, htab_t sys_ins_regs, bool sysreg128_p)
if (!o || (sysreg128_p && !aarch64_sys_reg_128bit_p (o->flags)))
return NULL;
- if (!aarch64_sys_ins_reg_supported_p (cpu_variant, o->name, &o->features))
+ set = o->features;
+ if (*q == '\0' && aarch64_sys_ins_reg_tlbid_xt (o))
+ {
+ aarch64_feature_set feat = AARCH64_FEATURE (TLBID);
+ AARCH64_CLEAR_FEATURES (set, set, feat);
+ }
+
+ if (!aarch64_sys_ins_reg_supported_p (cpu_variant, o->name, &set))
as_bad (_("selected processor does not support system register "
"name '%s'"), buf);
+
if (aarch64_sys_reg_deprecated_p (o->flags))
as_warn (_("system register name '%s' is deprecated and may be "
"removed in a future release"), buf);
@@ -11029,6 +11038,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"sve-b16mm", AARCH64_FEATURE (SVE_B16MM), AARCH64_FEATURE (SVE)},
{"mpamv2", AARCH64_FEATURE (MPAMv2), AARCH64_NO_FEATURES},
{"mtetc", AARCH64_FEATURE (MTETC), AARCH64_FEATURE (MEMTAG)},
+ {"tlbid", AARCH64_FEATURE (TLBID), AARCH64_NO_FEATURES},
{NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
};
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index fd5e6870d88..3ead6950fa8 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -388,6 +388,8 @@ automatically cause those extensions to be disabled.
@tab Enable SVE2.3.
@item @code{the} @tab
@tab Enable the Translation Hardening Extension.
+@item @code{tlbid} @tab
+ @tab Enable the TLBI Domains Extension.
@item @code{tme} @tab
@tab Enable the Transactional Memory Extension.
@item @code{tev} @tab
diff --git a/gas/testsuite/gas/aarch64/tlbid-1.d b/gas/testsuite/gas/aarch64/tlbid-1.d
new file mode 100644
index 00000000000..1149d42855c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tlbid-1.d
@@ -0,0 +1,32 @@
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*: d50c839f tlbi alle1is
+.*: d508831f tlbi vmalle1is
+.*: d50c839f tlbi alle1is
+.*: d508831f tlbi vmalle1is
+.*: d50c8380 tlbi alle1is, x0
+.*: d50c8300 tlbi alle2is, x0
+.*: d5088300 tlbi vmalle1is, x0
+.*: d50c83c0 tlbi vmalls12e1is, x0
+.*: d50c839e tlbi alle1is, x30
+.*: d50c831e tlbi alle2is, x30
+.*: d508831e tlbi vmalle1is, x30
+.*: d50c83de tlbi vmalls12e1is, x30
+.*: d50c8180 tlbi alle1os, x0
+.*: d50c8100 tlbi alle2os, x0
+.*: d5088100 tlbi vmalle1os, x0
+.*: d50c81c0 tlbi vmalls12e1os, x0
+.*: d50c8240 tlbi vmallws2e1is, x0
+.*: d50c8540 tlbi vmallws2e1os, x0
+.*: d50c819e tlbi alle1os, x30
+.*: d50c811e tlbi alle2os, x30
+.*: d508811e tlbi vmalle1os, x30
+.*: d50c81de tlbi vmalls12e1os, x30
+.*: d50c825e tlbi vmallws2e1is, x30
+.*: d50c855e tlbi vmallws2e1os, x30
diff --git a/gas/testsuite/gas/aarch64/tlbid-1.s b/gas/testsuite/gas/aarch64/tlbid-1.s
new file mode 100644
index 00000000000..390a62ae65c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tlbid-1.s
@@ -0,0 +1,28 @@
+ tlbi alle1is
+ tlbi vmalle1is
+ tlbi alle1is
+ tlbi vmalle1is
+
+ .arch armv8-a+tlbid
+ tlbi alle1is, x0
+ tlbi alle2is, x0
+ tlbi vmalle1is, x0
+ tlbi vmalls12e1is, x0
+ tlbi alle1is, x30
+ tlbi alle2is, x30
+ tlbi vmalle1is, x30
+ tlbi vmalls12e1is, x30
+
+ .arch armv9.4-a+tlbid
+ tlbi alle1os, x0
+ tlbi alle2os, x0
+ tlbi vmalle1os, x0
+ tlbi vmalls12e1os, x0
+ tlbi vmallws2e1is, x0
+ tlbi vmallws2e1os, x0
+ tlbi alle1os, x30
+ tlbi alle2os, x30
+ tlbi vmalle1os, x30
+ tlbi vmalls12e1os, x30
+ tlbi vmallws2e1is, x30
+ tlbi vmallws2e1os, x30
diff --git a/gas/testsuite/gas/aarch64/tlbid-invalid-1.d b/gas/testsuite/gas/aarch64/tlbid-invalid-1.d
new file mode 100644
index 00000000000..037ee49ae7a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tlbid-invalid-1.d
@@ -0,0 +1,3 @@
+#name: Test without +tlbid option.
+#as: -march=armv8-a
+#error_output: tlbid-invalid-1.l
diff --git a/gas/testsuite/gas/aarch64/tlbid-invalid-1.l b/gas/testsuite/gas/aarch64/tlbid-invalid-1.l
new file mode 100644
index 00000000000..49947a6aa1d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tlbid-invalid-1.l
@@ -0,0 +1,43 @@
+.*: Assembler messages:
+.*: Error: selected processor does not support system register name 'alle1is'
+.*: Error: selected processor does not support system register name 'alle2is'
+.*: Error: selected processor does not support system register name 'vmalle1is'
+.*: Error: selected processor does not support system register name 'vmalls12e1is'
+.*: Error: selected processor does not support system register name 'alle1is'
+.*: Error: operand mismatch -- `tlbi alle1is,w0'
+.*: Error: selected processor does not support system register name 'alle1is'
+.*: Info: did you mean this\?
+.*: Info: tlbi alle1is, x0
+.*: Error: selected processor does not support system register name 'alle2is'
+.*: Error: operand mismatch -- `tlbi alle2is,wzr'
+.*: Error: selected processor does not support system register name 'alle2is'
+.*: Info: did you mean this\?
+.*: Info: tlbi alle2is, xzr
+.*: Error: selected processor does not support system register name 'vmalle1is'
+.*: Error: operand mismatch -- `tlbi vmalle1is,w0'
+.*: Error: selected processor does not support system register name 'vmalle1is'
+.*: Info: did you mean this\?
+.*: Info: tlbi vmalle1is, x0
+.*: Error: selected processor does not support system register name 'vmalls12e1is'
+.*: Error: operand mismatch -- `tlbi vmalls12e1is,wzr'
+.*: Error: selected processor does not support system register name 'vmalls12e1is'
+.*: Info: did you mean this\?
+.*: Info: tlbi vmalls12e1is, xzr
+.*: Error: selected processor does not support system register name 'alle1os'
+.*: Error: selected processor does not support system register name 'alle2os'
+.*: Error: selected processor does not support system register name 'vmalle1os'
+.*: Error: selected processor does not support system register name 'vmalls12e1os'
+.*: Error: selected processor does not support system register name 'vmallws2e1is'
+.*: Error: selected processor does not support system register name 'vmallws2e1os'
+.*: Error: expected an integer or zero register at operand 2 -- `tlbi vmallws2e1os,x'
+.*: Error: selected processor does not support system register name 'alle1os'
+.*: Error: operand mismatch -- `tlbi alle1os,w30'
+.*: Error: selected processor does not support system register name 'alle1os'
+.*: Info: did you mean this\?
+.*: Info: tlbi alle1os, x30
+.*: Error: selected processor does not support system register name 'alle2os'
+.*: Error: expected an integer or zero register at operand 2 -- `tlbi alle2os,#30'
+.*: Error: selected processor does not support system register name 'vmalle1os'
+.*: Error: selected processor does not support system register name 'vmalls12e1os'
+.*: Error: selected processor does not support system register name 'vmallws2e1is'
+.*: Error: selected processor does not support system register name 'vmallws2e1os'
diff --git a/gas/testsuite/gas/aarch64/tlbid-invalid-1.s b/gas/testsuite/gas/aarch64/tlbid-invalid-1.s
new file mode 100644
index 00000000000..51ebd9aa8a4
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tlbid-invalid-1.s
@@ -0,0 +1,20 @@
+ tlbi alle1is, x0
+ tlbi alle2is, xzr
+ tlbi vmalle1is, x0
+ tlbi vmalls12e1is, xzr
+ tlbi alle1is, w0
+ tlbi alle2is, wzr
+ tlbi vmalle1is, w0
+ tlbi vmalls12e1is, wzr
+ tlbi alle1os, x0
+ tlbi alle2os, xzr
+ tlbi vmalle1os, x0
+ tlbi vmalls12e1os, xzr
+ tlbi vmallws2e1is, x0
+ tlbi vmallws2e1os, x
+ tlbi alle1os, w30
+ tlbi alle2os, #30
+ tlbi vmalle1os, x30
+ tlbi vmalls12e1os, x30
+ tlbi vmallws2e1is, x30
+ tlbi vmallws2e1os, x30
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 42ff6eff26d..640f6c4c5fb 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -287,6 +287,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_MPAMv2,
/* MTETC. */
AARCH64_FEATURE_MTETC,
+ /* TLBI Domains. */
+ AARCH64_FEATURE_TLBID,
/* Virtual features. These are used to gate instructions that are enabled
by either of two (or more) sets of command line flags. */
@@ -1670,6 +1672,7 @@ typedef struct
} aarch64_sys_ins_reg;
extern bool aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
+extern bool aarch64_sys_ins_reg_tlbid_xt (const aarch64_sys_ins_reg *);
extern bool
aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
const char *reg_name,
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 552be689da8..310a62220cf 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -330,7 +330,12 @@ aarch64_ext_regrt_sysins (const aarch64_operand *self, aarch64_opnd_info *info,
/* This will make the constraint checking happy and more importantly will
help the disassembler determine whether this operand is optional or
not. */
- info->present = aarch64_sys_ins_reg_has_xt (inst->operands[0].sysins_op);
+
+ if (aarch64_sys_ins_reg_tlbid_xt (inst->operands[0].sysins_op)
+ && info->reg.regno != 31)
+ info->present = true;
+ else
+ info->present = aarch64_sys_ins_reg_has_xt (inst->operands[0].sysins_op);
return true;
}
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 67b6e67dde8..e76afe449d6 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -1854,18 +1854,21 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
{
assert (idx == 1 && (aarch64_get_operand_class (opnds[0].type)
== AARCH64_OPND_CLASS_SYSTEM));
- if (opnds[1].present
- && !aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
+ if (!(opnds[1].present && aarch64_sys_ins_reg_tlbid_xt (opnds[0].sysins_op)))
{
- set_other_error (mismatch_detail, idx, _("extraneous register"));
- return false;
- }
- if (!opnds[1].present
- && aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
- {
- set_other_error (mismatch_detail, idx, _("missing register"));
- return false;
- }
+ if (opnds[1].present
+ && !aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
+ {
+ set_other_error (mismatch_detail, idx, _("extraneous register"));
+ return false;
+ }
+ if (!opnds[1].present
+ && aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
+ {
+ set_other_error (mismatch_detail, idx, _("missing register"));
+ return false;
+ }
+ }
}
switch (qualifier)
{
@@ -5382,16 +5385,25 @@ const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[] =
{ "paall", CPENS (6, C8, C7, 4), 0, AARCH64_NO_FEATURES },
#define TLBI_XS_OP(OP, CODE, FLAGS) \
- { OP, CODE, FLAGS, AARCH64_NO_FEATURES }, \
- { OP "nxs", CODE | CPENS (0, C9, 0, 0), FLAGS, AARCH64_FEATURE (XS) },
+ { OP, CODE, FLAGS, AARCH64_FEATURE (TLBID)}, \
+ { OP "nxs", CODE | CPENS (0, C9, 0, 0), FLAGS, AARCH64_FEATURES (2, XS, TLBID)},
+
+ TLBI_XS_OP ( "vmalle1is", CPENS (0, C8, C3, 0), F_TLBID_XT)
+ TLBI_XS_OP ( "vmalls12e1is",CPENS(4,C8, C3, 6), F_TLBID_XT)
+ TLBI_XS_OP ( "alle2is", CPENS (4, C8, C3, 0), F_TLBID_XT)
+ TLBI_XS_OP ( "alle1is", CPENS (4, C8, C3, 4), F_TLBID_XT)
+#undef TLBI_XS_OP
+
+#define TLBI_XS_OP(OP, CODE, FLAGS) \
+ { OP, CODE, FLAGS, AARCH64_NO_FEATURES}, \
+ { OP "nxs", CODE | CPENS (0, C9, 0, 0), FLAGS, AARCH64_FEATURE (XS)},
TLBI_XS_OP ( "vmalle1", CPENS (0, C8, C7, 0), 0)
TLBI_XS_OP ( "vae1", CPENS (0, C8, C7, 1), F_HASXT | F_REG_128)
- TLBI_XS_OP ( "aside1", CPENS (0, C8, C7, 2), F_HASXT )
+ TLBI_XS_OP ( "aside1", CPENS (0, C8, C7, 2), F_HASXT)
TLBI_XS_OP ( "vaae1", CPENS (0, C8, C7, 3), F_HASXT | F_REG_128)
- TLBI_XS_OP ( "vmalle1is", CPENS (0, C8, C3, 0), 0)
TLBI_XS_OP ( "vae1is", CPENS (0, C8, C3, 1), F_HASXT | F_REG_128)
- TLBI_XS_OP ( "aside1is", CPENS (0, C8, C3, 2), F_HASXT )
+ TLBI_XS_OP ( "aside1is", CPENS (0, C8, C3, 2), F_HASXT)
TLBI_XS_OP ( "vaae1is", CPENS (0, C8, C3, 3), F_HASXT | F_REG_128)
TLBI_XS_OP ( "ipas2e1is", CPENS (4, C8, C0, 1), F_HASXT | F_REG_128)
TLBI_XS_OP ( "ipas2le1is",CPENS (4, C8, C0, 5), F_HASXT | F_REG_128)
@@ -5400,13 +5412,10 @@ const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[] =
TLBI_XS_OP ( "vae2", CPENS (4, C8, C7, 1), F_HASXT | F_REG_128)
TLBI_XS_OP ( "vae2is", CPENS (4, C8, C3, 1), F_HASXT | F_REG_128)
TLBI_XS_OP ( "vmalls12e1",CPENS (4, C8, C7, 6), 0)
- TLBI_XS_OP ( "vmalls12e1is",CPENS(4,C8, C3, 6), 0)
TLBI_XS_OP ( "vae3", CPENS (6, C8, C7, 1), F_HASXT | F_REG_128)
TLBI_XS_OP ( "vae3is", CPENS (6, C8, C3, 1), F_HASXT | F_REG_128)
TLBI_XS_OP ( "alle2", CPENS (4, C8, C7, 0), 0)
- TLBI_XS_OP ( "alle2is", CPENS (4, C8, C3, 0), 0)
TLBI_XS_OP ( "alle1", CPENS (4, C8, C7, 4), 0)
- TLBI_XS_OP ( "alle1is", CPENS (4, C8, C3, 4), 0)
TLBI_XS_OP ( "alle3", CPENS (6, C8, C7, 0), 0)
TLBI_XS_OP ( "alle3is", CPENS (6, C8, C3, 0), 0)
TLBI_XS_OP ( "vale1is", CPENS (0, C8, C3, 5), F_HASXT | F_REG_128)
@@ -5417,15 +5426,26 @@ const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[] =
TLBI_XS_OP ( "vale2", CPENS (4, C8, C7, 5), F_HASXT | F_REG_128)
TLBI_XS_OP ( "vale3", CPENS (6, C8, C7, 5), F_HASXT | F_REG_128)
TLBI_XS_OP ( "vaale1", CPENS (0, C8, C7, 7), F_HASXT | F_REG_128)
+#undef TLBI_XS_OP
+#define TLBI_XS_OP(OP, CODE, FLAGS) \
+ { OP, CODE, FLAGS, AARCH64_FEATURES (2, V8_4A, TLBID)}, \
+ { OP "nxs", CODE | CPENS (0, C9, 0, 0), FLAGS, AARCH64_FEATURES (2, XS, TLBID)},
+
+ TLBI_XS_OP ( "vmalle1os", CPENS (0, C8, C1, 0), F_TLBID_XT)
+ TLBI_XS_OP ( "vmalls12e1os", CPENS (4, C8, C1, 6), F_TLBID_XT)
+ TLBI_XS_OP ( "alle2os", CPENS (4, C8, C1, 0), F_TLBID_XT)
+ TLBI_XS_OP ( "alle1os", CPENS (4, C8, C1, 4), F_TLBID_XT)
+ TLBI_XS_OP ( "vmallws2e1is", CPENS (4, C8, C2, 2), F_TLBID_XT)
+ TLBI_XS_OP ( "vmallws2e1os", CPENS (4, C8, C5, 2), F_TLBID_XT)
#undef TLBI_XS_OP
+
#define TLBI_XS_OP(OP, CODE, FLAGS) \
- { OP, CODE, FLAGS, AARCH64_FEATURE (V8_4A) }, \
- { OP "nxs", CODE | CPENS (0, C9, 0, 0), FLAGS, AARCH64_FEATURE (XS) },
+ { OP, CODE, FLAGS, AARCH64_FEATURE (V8_4A)}, \
+ { OP "nxs", CODE | CPENS (0, C9, 0, 0), FLAGS, AARCH64_FEATURE (XS)},
- TLBI_XS_OP ( "vmalle1os", CPENS (0, C8, C1, 0), 0 )
TLBI_XS_OP ( "vae1os", CPENS (0, C8, C1, 1), F_HASXT | F_REG_128 )
- TLBI_XS_OP ( "aside1os", CPENS (0, C8, C1, 2), F_HASXT )
+ TLBI_XS_OP ( "aside1os", CPENS (0, C8, C1, 2), F_HASXT)
TLBI_XS_OP ( "vaae1os", CPENS (0, C8, C1, 3), F_HASXT | F_REG_128 )
TLBI_XS_OP ( "vale1os", CPENS (0, C8, C1, 5), F_HASXT | F_REG_128 )
TLBI_XS_OP ( "vaale1os", CPENS (0, C8, C1, 7), F_HASXT | F_REG_128 )
@@ -5433,12 +5453,9 @@ const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[] =
TLBI_XS_OP ( "ipas2le1os", CPENS (4, C8, C4, 4), F_HASXT | F_REG_128 )
TLBI_XS_OP ( "vae2os", CPENS (4, C8, C1, 1), F_HASXT | F_REG_128 )
TLBI_XS_OP ( "vale2os", CPENS (4, C8, C1, 5), F_HASXT | F_REG_128 )
- TLBI_XS_OP ( "vmalls12e1os", CPENS (4, C8, C1, 6), 0 )
TLBI_XS_OP ( "vae3os", CPENS (6, C8, C1, 1), F_HASXT | F_REG_128 )
TLBI_XS_OP ( "vale3os", CPENS (6, C8, C1, 5), F_HASXT | F_REG_128 )
- TLBI_XS_OP ( "alle2os", CPENS (4, C8, C1, 0), 0 )
- TLBI_XS_OP ( "alle1os", CPENS (4, C8, C1, 4), 0 )
- TLBI_XS_OP ( "alle3os", CPENS (6, C8, C1, 0), 0 )
+ TLBI_XS_OP ( "alle3os", CPENS (6, C8, C1, 0), 0)
TLBI_XS_OP ( "rvae1", CPENS (0, C8, C6, 1), F_HASXT | F_REG_128 )
TLBI_XS_OP ( "rvaae1", CPENS (0, C8, C6, 3), F_HASXT | F_REG_128 )
@@ -5470,6 +5487,7 @@ const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[] =
TLBI_XS_OP ( "rvale3is", CPENS (6, C8, C2, 5), F_HASXT | F_REG_128 )
TLBI_XS_OP ( "rvae3os", CPENS (6, C8, C5, 1), F_HASXT | F_REG_128 )
TLBI_XS_OP ( "rvale3os", CPENS (6, C8, C5, 5), F_HASXT | F_REG_128 )
+ TLBI_XS_OP ( "vmallws2e1",CPENS (4, C8, C6, 3), 0)
#undef TLBI_XS_OP
@@ -5582,6 +5600,12 @@ aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *sys_ins_reg)
return (sys_ins_reg->flags & F_HASXT) != 0;
}
+bool
+aarch64_sys_ins_reg_tlbid_xt (const aarch64_sys_ins_reg *sys_ins_reg)
+{
+ return (sys_ins_reg->flags & F_TLBID_XT) != 0;
+}
+
extern bool
aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
const char *reg_name,
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index a612c3a3db9..17bbaaa4a55 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -364,6 +364,9 @@ verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
#undef F_REG_128
#define F_REG_128 (1 << 7) /* System register implementable as 128-bit wide. */
+#undef F_TLBID_XT
+#define F_TLBID_XT (1 << 8) /* System instruction register <Xt> as optional operand. */
+
/* PSTATE field name for the MSR instruction this is encoded in "op1:op2:CRm".
Part of CRm can be used to encode <pstatefield>. E.g. CRm[3:1] for SME.
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