[binutils-gdb] PowerPC: Support for eTCE (RFC02662)

[Abhay Kandpal]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=7103202e6068ff3891d71dbfaf236e58945fb098

commit 7103202e6068ff3891d71dbfaf236e58945fb098
Author: Abhay Kandpal <abhay@linux.ibm.com>
Date:   Tue Jan 13 00:28:45 2026 -0500

    PowerPC: Support for eTCE (RFC02662)
    
    opcodes/
            * ppc-opc.c (XTLBIE_MASK, XTLBIEIO_MASK): New macros.
            (powerpc_opcodes): Add tlbiep, tlbieio, tlbsyncio,
            ptesyncio.
    
    gas/
            * testsuite/gas/ppc/future.s: New test.
            * testsuite/gas/ppc/future.d: Likewise.

Diff:
---
 gas/testsuite/gas/ppc/future.d |  5 +++++
 gas/testsuite/gas/ppc/future.s |  5 +++++
 opcodes/ppc-opc.c              | 13 +++++++++++++
 3 files changed, 23 insertions(+)

diff --git a/gas/testsuite/gas/ppc/future.d b/gas/testsuite/gas/ppc/future.d
index 5c8fe7fe6ed..facba4365b9 100644
--- a/gas/testsuite/gas/ppc/future.d
+++ b/gas/testsuite/gas/ppc/future.d
@@ -131,4 +131,9 @@ Disassembly of section \.text:
 .*:	(a6 c2 89 7e|7e 89 c2 a6) 	mfupmc7 r20
 .*:	(a6 c2 aa 7e|7e aa c2 a6) 	mfupmc8 r21
 .*:	(a6 c2 ca 7e|7e ca c2 a6) 	mfupmc8 r22
+.*:	(64 10 8f 7c|7c 8f 10 64) 	tlbiep  r2,r4,3,1,1
+.*:	(64 10 60 7c|7c 60 10 64) 	tlbiep  r2,r3
+.*:	(24 38 c8 7c|7c c8 38 24) 	tlbieio r7,r6,2
+.*:	(68 04 20 7d|7d 20 04 68) 	tlbsyncio r9
+.*:	(a8 04 a0 7c|7c a0 04 a8) 	ptesyncio r5
 #pass
diff --git a/gas/testsuite/gas/ppc/future.s b/gas/testsuite/gas/ppc/future.s
index 5cb2305fb30..f265928fcb7 100644
--- a/gas/testsuite/gas/ppc/future.s
+++ b/gas/testsuite/gas/ppc/future.s
@@ -105,4 +105,9 @@ _start:
 	mfpmc7 20
 	mfupmc8 21
 	mfpmc8 22
+	tlbiep 2, 4, 3, 1, 1
+	tlbiep 2, 3
+	tlbieio 7, 6, 2
+	tlbsyncio 9
+	ptesyncio 5
 
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index d1e0f8f5b57..dfc6734e027 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -4628,6 +4628,12 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);
    field.  */
 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
 
+/* The mask of TLB invalidate Entry with 20th bit specified.  */
+#define XTLBIE_MASK (X_MASK | (1<<20))
+
+/* The mask of TLB invalidate Entry for I/O device.  */
+#define XTLBIEIO_MASK (XTLBIE_MASK | (3<<16))
+
 /* An X form wait instruction with everything filled in except the WC
    and PL fields.  */
 #define XWCPL_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | (3 << 18) | RB_MASK)
@@ -7238,6 +7244,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"iseleq",	XISEL(31,15,2),	X_MASK,	     PPCISEL,	EXT,		{RT, RA0, RB}},
 {"isel",	XISEL(31,15,0), XISEL_MASK, PPCISEL|TITAN, 0,		{RT, RA0, RB, BC}},
 
+{"tlbieio",	X(31,18), 	XTLBIEIO_MASK, FUTURE,	0,		{RB, RS, RIC}},
 {"tlbilxlpid",	XTO(31,18,0),	XTO_MASK, E500MC|PPCA2,	0,		{0}},
 {"tlbilxpid",	XTO(31,18,1),	XTO_MASK, E500MC|PPCA2,	0,		{0}},
 {"tlbilxva",	XTO(31,18,3),	XTO_MASK, E500MC|PPCA2,	0,		{RA0, RB}},
@@ -7297,6 +7304,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"mviwsplt",	X(31,46),	X_MASK,	     E6500,	0,		{VD, RA, RB}},
 
+{"tlbiep",	X(31,50),	XTLBIE_MASK, FUTURE,	TITAN,		{RB, RS, RIC, PRS, X_R}},
+
 {"lvewx",	X(31,71),	X_MASK,	     PPCVEC,	0,		{VD, RA0, RB}},
 
 {"addg6s",	XO(31,74,0,0),	XO_MASK,     POWER6,	0,		{RT, RA, RB}},
@@ -8627,6 +8636,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"lxvrll",	X(31,557),	XX1_MASK,    PPCVSXF,	0,		{XT6, RA0, RB}},
 
+{"tlbsyncio",	X(31,564),	XRARB_MASK,  FUTURE,	0,		{RS}},
+
 {"tlbsync",	X(31,566),	0xffffffff,  PPC,	0,		{0}},
 
 {"lfsux",	X(31,567),	X_MASK,	     COM,	PPCEFS,		{FRT, RAS, RB}},
@@ -8652,6 +8663,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"mfsr",	X(31,595), XRB_MASK|(1<<20), COM,	NON32,		{RT, SR}},
 
+{"ptesyncio",	X(31,596),	XRARB_MASK,  FUTURE,	0,		{RS}},
+
 {"lswi",	X(31,597),	X_MASK,	     PPCCOM,	E500|E500MC,	{RT, RAX, NBI}},
 {"lsi",		X(31,597),	X_MASK,	     PWRCOM,	0,		{RT, RA0, NB}},