[binutils-gdb] aarch64: Add support for FEAT_TPS and FEAT_TPSP system registers

[SRINATH PARVATHANENI]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=4e814456932cd89681fd52d9d1709dca2b6e2705

commit 4e814456932cd89681fd52d9d1709dca2b6e2705
Author: Srinath Parvathaneni <srinath.parvathaneni@arm.com>
Date:   Wed Jan 7 17:19:13 2026 +0000

    aarch64: Add support for FEAT_TPS and FEAT_TPSP system registers
    
    This patch adds support for TPMIN*/TPMAX* system registers
    as part of POE2 extension.

Diff:
---
 gas/testsuite/gas/aarch64/sysreg/sysreg-12.d | 40 ++++++++++++++++++++++++++++
 gas/testsuite/gas/aarch64/sysreg/sysreg-12.s | 18 +++++++++++++
 opcodes/aarch64-sys-regs.def                 | 16 +++++++++++
 3 files changed, 74 insertions(+)

diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-12.d b/gas/testsuite/gas/aarch64/sysreg/sysreg-12.d
new file mode 100644
index 00000000000..595a6ae020f
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-12.d
@@ -0,0 +1,40 @@
+#as: -I$srcdir/$subdir
+#objdump: -dr
+
+.*:     file format .*
+
+[^:]+:
+
+0+ <.*>:
+.*:	d51b22a0 	msr	tpmax0_el0, x0
+.*:	d53b22a0 	mrs	x0, tpmax0_el0
+.*:	d51822a0 	msr	tpmax0_el1, x0
+.*:	d53822a0 	mrs	x0, tpmax0_el1
+.*:	d51d22a0 	msr	tpmax0_el12, x0
+.*:	d53d22a0 	mrs	x0, tpmax0_el12
+.*:	d51c22a0 	msr	tpmax0_el2, x0
+.*:	d53c22a0 	mrs	x0, tpmax0_el2
+.*:	d51b22e0 	msr	tpmax1_el0, x0
+.*:	d53b22e0 	mrs	x0, tpmax1_el0
+.*:	d51822e0 	msr	tpmax1_el1, x0
+.*:	d53822e0 	mrs	x0, tpmax1_el1
+.*:	d51d22e0 	msr	tpmax1_el12, x0
+.*:	d53d22e0 	mrs	x0, tpmax1_el12
+.*:	d51c22e0 	msr	tpmax1_el2, x0
+.*:	d53c22e0 	mrs	x0, tpmax1_el2
+.*:	d51b2280 	msr	tpmin0_el0, x0
+.*:	d53b2280 	mrs	x0, tpmin0_el0
+.*:	d5182280 	msr	tpmin0_el1, x0
+.*:	d5382280 	mrs	x0, tpmin0_el1
+.*:	d51d2280 	msr	tpmin0_el12, x0
+.*:	d53d2280 	mrs	x0, tpmin0_el12
+.*:	d51c2280 	msr	tpmin0_el2, x0
+.*:	d53c2280 	mrs	x0, tpmin0_el2
+.*:	d51b22c0 	msr	tpmin1_el0, x0
+.*:	d53b22c0 	mrs	x0, tpmin1_el0
+.*:	d51822c0 	msr	tpmin1_el1, x0
+.*:	d53822c0 	mrs	x0, tpmin1_el1
+.*:	d51d22c0 	msr	tpmin1_el12, x0
+.*:	d53d22c0 	mrs	x0, tpmin1_el12
+.*:	d51c22c0 	msr	tpmin1_el2, x0
+.*:	d53c22c0 	mrs	x0, tpmin1_el2
diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-12.s b/gas/testsuite/gas/aarch64/sysreg/sysreg-12.s
new file mode 100644
index 00000000000..02a55fc788d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-12.s
@@ -0,0 +1,18 @@
+.include "sysreg-test-utils.inc"
+
+	rw_sys_reg tpmax0_el0
+	rw_sys_reg tpmax0_el1
+	rw_sys_reg tpmax0_el12
+	rw_sys_reg tpmax0_el2
+	rw_sys_reg tpmax1_el0
+	rw_sys_reg tpmax1_el1
+	rw_sys_reg tpmax1_el12
+	rw_sys_reg tpmax1_el2
+	rw_sys_reg tpmin0_el0
+	rw_sys_reg tpmin0_el1
+	rw_sys_reg tpmin0_el12
+	rw_sys_reg tpmin0_el2
+	rw_sys_reg tpmin1_el0
+	rw_sys_reg tpmin1_el1
+	rw_sys_reg tpmin1_el12
+	rw_sys_reg tpmin1_el2
diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def
index 0d807e2bab0..1eff9a9e3f8 100644
--- a/opcodes/aarch64-sys-regs.def
+++ b/opcodes/aarch64-sys-regs.def
@@ -1356,6 +1356,22 @@
   SYSREG ("tpidr_el2",		CPENC (3,4,13,0,2),	0,		AARCH64_NO_FEATURES)
   SYSREG ("tpidr_el3",		CPENC (3,6,13,0,2),	0,		AARCH64_NO_FEATURES)
   SYSREG ("tpidrro_el0",	CPENC (3,3,13,0,3),	0,		AARCH64_NO_FEATURES)
+  SYSREG ("tpmax0_el0",		CPENC (3,3,2,2,5),	0,		AARCH64_NO_FEATURES)
+  SYSREG ("tpmax0_el1",		CPENC (3,0,2,2,5),	0,		AARCH64_NO_FEATURES)
+  SYSREG ("tpmax0_el12",	CPENC (3,5,2,2,5),	0,		AARCH64_NO_FEATURES)
+  SYSREG ("tpmax0_el2",		CPENC (3,4,2,2,5),	0,		AARCH64_NO_FEATURES)
+  SYSREG ("tpmax1_el0",		CPENC (3,3,2,2,7),	0,		AARCH64_NO_FEATURES)
+  SYSREG ("tpmax1_el1",		CPENC (3,0,2,2,7),	0,		AARCH64_NO_FEATURES)
+  SYSREG ("tpmax1_el12",	CPENC (3,5,2,2,7),	0,		AARCH64_NO_FEATURES)
+  SYSREG ("tpmax1_el2",		CPENC (3,4,2,2,7),	0,		AARCH64_NO_FEATURES)
+  SYSREG ("tpmin0_el0",		CPENC (3,3,2,2,4),	0,		AARCH64_NO_FEATURES)
+  SYSREG ("tpmin0_el1",		CPENC (3,0,2,2,4),	0,		AARCH64_NO_FEATURES)
+  SYSREG ("tpmin0_el12",	CPENC (3,5,2,2,4),	0,		AARCH64_NO_FEATURES)
+  SYSREG ("tpmin0_el2",		CPENC (3,4,2,2,4),	0,		AARCH64_NO_FEATURES)
+  SYSREG ("tpmin1_el0",		CPENC (3,3,2,2,6),	0,		AARCH64_NO_FEATURES)
+  SYSREG ("tpmin1_el1",		CPENC (3,0,2,2,6),	0,		AARCH64_NO_FEATURES)
+  SYSREG ("tpmin1_el12",	CPENC (3,5,2,2,6),	0,		AARCH64_NO_FEATURES)
+  SYSREG ("tpmin1_el2",		CPENC (3,4,2,2,6),	0,		AARCH64_NO_FEATURES)
   SYSREG ("trbbaser_el1",	CPENC (3,0,9,11,2),	0,		AARCH64_FEATURE (V9A)) /* TRBE */
   SYSREG ("trbidr_el1",		CPENC (3,0,9,11,7),	F_REG_READ,	AARCH64_FEATURE (V9A)) /* TRBE */
   SYSREG ("trblimitr_el1",	CPENC (3,0,9,11,0),	0,		AARCH64_FEATURE (V9A)) /* TRBE */