[binutils-gdb] aarch64: Remove teecr32_el1 and teehbr32_el1

Alice Carlotti acarlotti@sourceware.org
Tue Sep 23 19:08:38 GMT 2025


https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=8c0024ca8f6c01fc45f081f5ef11c9a6a1c24eb0

commit 8c0024ca8f6c01fc45f081f5ef11c9a6a1c24eb0
Author: Alice Carlotti <alice.carlotti@arm.com>
Date:   Tue Sep 2 17:29:33 2025 +0100

    aarch64: Remove teecr32_el1 and teehbr32_el1
    
    These system registers were removed from the architecture over a decade
    ago, so there's no need to continue supporting them.

Diff:
---
 gas/testsuite/gas/aarch64/sysreg/sysreg-1.d | 4 ----
 gas/testsuite/gas/aarch64/sysreg/sysreg-1.s | 3 ---
 opcodes/aarch64-sys-regs.def                | 2 --
 3 files changed, 9 deletions(-)

diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-1.d b/gas/testsuite/gas/aarch64/sysreg/sysreg-1.d
index 6e247a7a692..b991390b0eb 100644
--- a/gas/testsuite/gas/aarch64/sysreg/sysreg-1.d
+++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-1.d
@@ -24,10 +24,6 @@ Disassembly of section \.text:
  *[0-9a-f]+:	d5340707 	mrs	x7, dbgvcr32_el2
  *[0-9a-f]+:	d51c5307 	msr	fpexc32_el2, x7
  *[0-9a-f]+:	d53c5307 	mrs	x7, fpexc32_el2
- *[0-9a-f]+:	d5120007 	msr	teecr32_el1, x7
- *[0-9a-f]+:	d5320007 	mrs	x7, teecr32_el1
- *[0-9a-f]+:	d5121007 	msr	teehbr32_el1, x7
- *[0-9a-f]+:	d5321007 	mrs	x7, teehbr32_el1
  *[0-9a-f]+:	d51be207 	msr	cntp_tval_el0, x7
  *[0-9a-f]+:	d53be207 	mrs	x7, cntp_tval_el0
  *[0-9a-f]+:	d51be227 	msr	cntp_ctl_el0, x7
diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-1.s b/gas/testsuite/gas/aarch64/sysreg/sysreg-1.s
index b9060361ff0..d28efa557a2 100644
--- a/gas/testsuite/gas/aarch64/sysreg/sysreg-1.s
+++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-1.s
@@ -38,9 +38,6 @@
 
 	rw_sys_reg sys_reg=fpexc32_el2 xreg=x7
 
-	rw_sys_reg sys_reg=teecr32_el1 xreg=x7
-	rw_sys_reg sys_reg=teehbr32_el1 xreg=x7
-
 	rw_sys_reg sys_reg=cntp_tval_el0 xreg=x7
 	rw_sys_reg sys_reg=cntp_ctl_el0 xreg=x7
 	rw_sys_reg sys_reg=cntp_cval_el0 xreg=x7
diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def
index 7c606013175..521faf92ec0 100644
--- a/opcodes/aarch64-sys-regs.def
+++ b/opcodes/aarch64-sys-regs.def
@@ -1025,8 +1025,6 @@
   SYSREG ("tcrmask_el1",	CPENC (3,0,2,7,2),	0,		AARCH64_FEATURE (V9_5A)) /* SRMASK */
   SYSREG ("tcrmask_el12",	CPENC (3,5,2,7,2),	0,		AARCH64_FEATURE (V9_5A)) /* SRMASK */
   SYSREG ("tcrmask_el2",	CPENC (3,4,2,7,2),	0,		AARCH64_FEATURE (V9_5A)) /* SRMASK */
-  SYSREG ("teecr32_el1",	CPENC (2,2,0,0,0),	0,		AARCH64_NO_FEATURES)
-  SYSREG ("teehbr32_el1",	CPENC (2,2,1,0,0),	0,		AARCH64_NO_FEATURES)
   SYSREG ("tfsr_el1",		CPENC (3,0,5,6,0),	0,		AARCH64_FEATURE (MEMTAG))
   SYSREG ("tfsr_el12",		CPENC (3,5,5,6,0),	0,		AARCH64_FEATURE (MEMTAG))
   SYSREG ("tfsr_el2",		CPENC (3,4,5,6,0),	0,		AARCH64_FEATURE (MEMTAG))


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