[binutils-gdb] gas: aarch64: Add flag for GICv5

[Saurabh Jha]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=c3954fc3a14ba01def0bcc278d81c7c9e5994365

commit c3954fc3a14ba01def0bcc278d81c7c9e5994365
Author: Saurabh Jha <saurabh.jha@arm.com>
Date:   Fri Jul 18 14:32:23 2025 +0000

    gas: aarch64: Add flag for GICv5
    
    Generic Interrupt Controller v5, GICv5, adds new system registers
    and system instructions. These are enabled with the +gcie flag, where
    gcie stands for GICv5 (Generic Interrupt Controller) CPU Interrupt
    Extension.

Diff:
---
 gas/config/tc-aarch64.c  | 1 +
 gas/doc/c-aarch64.texi   | 2 ++
 include/opcode/aarch64.h | 2 ++
 opcodes/aarch64-tbl.h    | 3 +++
 4 files changed, 8 insertions(+)

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 08f995dbb45..3687271ff7a 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10858,6 +10858,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
   {"pops",		AARCH64_FEATURE (PoPS), AARCH64_NO_FEATURES},
   {"sve2p2",		AARCH64_FEATURE (SVE2p2), AARCH64_FEATURE (SVE2p1)},
   {"sme2p2",		AARCH64_FEATURE (SME2p2), AARCH64_FEATURE (SME2p1)},
+  {"gcie",		AARCH64_FEATURE (GCIE), AARCH64_NO_FEATURES},
   {NULL,		AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
 };
 
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 8f5702f5b13..1cbd97795fa 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -223,6 +223,8 @@ automatically cause those extensions to be disabled.
  @tab Enable Armv9.6 fprcvt instructions.
 @item @code{frintts} @tab @code{fp}
  @tab Enable floating-point round to integral value instructions.
+@item @code{gcie} @tab
+ @tab Enable the GICv5 (Generic Interrupt Controller) CPU Interface Extension.
 @item @code{gcs} @tab
  @tab Enable the Guarded Control Stack Extension.
 @item @code{hbc} @tab
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index bc5ac363fd8..8a771a13012 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -251,6 +251,8 @@ enum aarch64_feature_bit {
   AARCH64_FEATURE_FPRCVT,
   /* Point of Physical Storage.  */
   AARCH64_FEATURE_PoPS,
+  /* GICv5 (Generic Interrupt Controller) CPU Interface Extension.  */
+  AARCH64_FEATURE_GCIE,
 
   /* Virtual features.  These are used to gate instructions that are enabled
      by either of two (or more) sets of command line flags.  */
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 0ae7342e2e1..34b551eb64c 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -3009,6 +3009,8 @@ static const aarch64_feature_set aarch64_feature_sve_sme2p2 =
   AARCH64_FEATURE (SVE_SME2p2);
 static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 =
   AARCH64_FEATURE (SVE2p2_SME2p2);
+static const aarch64_feature_set aarch64_feature_gcie =
+  AARCH64_FEATURE (GCIE);
 
 #define CORE		&aarch64_feature_v8
 #define FP		&aarch64_feature_fp
@@ -3119,6 +3121,7 @@ static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 =
 #define SME2p2		&aarch64_feature_sme2p2
 #define SVE_SME2p2	&aarch64_feature_sve_sme2p2
 #define SVE2p2_SME2p2	&aarch64_feature_sve2p2_sme2p2
+#define GCIE		&aarch64_feature_gcie
 
 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }