[binutils-gdb] RISC-V: Add implicit dependency to the XTheadVector extension

[Tsukasa OI]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=ed57ac46e53a71c463c0f7510d4e3bb5aac675ab

commit ed57ac46e53a71c463c0f7510d4e3bb5aac675ab
Author: Tsukasa OI <research_trasio@irq.a4lg.com>
Date:   Sun May 18 04:35:16 2025 +0000

    RISC-V: Add implicit dependency to the XTheadVector extension
    
    While this dependency is not directly stated in the documentation,
    the XTheadVector extension cannot work without the Zicsr extension
    (the documentation does not specify CSR access instruction subset
    either as in the Zkr extension or the seed CSR section in the manual).
    
    Also, making an implication to the Zicsr extension is in parity with
    the ratified vector extensions (in GNU Binutils, the Zve32x extension --
    a dependency of V -- depends on the Zvl32b and Zicsr extensions).
    
    This commit adds this implicit dependency.
    
    bfd/ChangeLog:
    
            * elfxx-riscv.c (riscv_implicit_subsets): Add implicit
            dependency "XTheadVector" -> "Zicsr".
    
    gas/ChangeLog:
    
            * testsuite/gas/riscv/imply.s: Add implicit "XTheadVector"
            dependency to the "Zicsr" extension.
            * testsuite/gas/riscv/imply.d: Ditto.

Diff:
---
 bfd/elfxx-riscv.c               | 2 ++
 gas/testsuite/gas/riscv/imply.d | 1 +
 gas/testsuite/gas/riscv/imply.s | 2 ++
 3 files changed, 5 insertions(+)

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index cdcbcd7a29b..2487beeecc5 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1206,6 +1206,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"xsfvqmaccdod", "+zve32x,+zvl128b", check_implicit_always},
   {"xsfvfnrclipxfqf", "+zve32f", check_implicit_always},
 
+  {"xtheadvector", "+zicsr", check_implicit_always},
+
   {"v", "+zve64d,+zvl128b", check_implicit_always},
   {"zvfh", "+zvfhmin,+zfhmin", check_implicit_always},
   {"zvfhmin", "+zve32f", check_implicit_always},
diff --git a/gas/testsuite/gas/riscv/imply.d b/gas/testsuite/gas/riscv/imply.d
index bce97ddf471..58f13e488cf 100644
--- a/gas/testsuite/gas/riscv/imply.d
+++ b/gas/testsuite/gas/riscv/imply.d
@@ -22,6 +22,7 @@ SYMBOL TABLE:
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvl32b1p0_xsfvfnrclipxfqf1p0
+[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_xtheadvector1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfhmin1p0_zvl32b1p0
diff --git a/gas/testsuite/gas/riscv/imply.s b/gas/testsuite/gas/riscv/imply.s
index c047ed6b758..fc5cd500775 100644
--- a/gas/testsuite/gas/riscv/imply.s
+++ b/gas/testsuite/gas/riscv/imply.s
@@ -25,6 +25,8 @@ imply xsfvqmaccqoq
 imply xsfvqmaccdod
 imply xsfvfnrclipxfqf
 
+imply xtheadvector
+
 imply v
 imply zvfh
 imply zvfhmin